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    SRAM WITH HIERARCHICAL BIT LINES IN MONOLITHIC 3D INTEGRATED CHIPS
    32.
    发明申请
    SRAM WITH HIERARCHICAL BIT LINES IN MONOLITHIC 3D INTEGRATED CHIPS 审中-公开

    公开(公告)号：US20190273084A1

    公开(公告)日：2019-09-05

    申请号：US16349242

    申请日：2016-12-29

    Applicant: INTEL CORPORATION

    Inventor： Yih Wang

    IPC: H01L27/11 ,  H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H01L21/768 ,  H01L21/311

    Abstract: A memory device includes a first plurality of memory cells, a second plurality of memory cells, and a local sense amplifier between the first plurality of memory cells and the second plurality of memory cells, all on a first level, and a local bit line on a second level. The second level is vertically separated by one or more first inter-level dielectric layers from the first level in a first direction and the local bit line is electrically coupled to each memory cell of the first plurality of memory cells and the second plurality of memory cells, as well as the local sense amplifier. The memory device also includes a global bit line on a third level vertically separated by one or more inter-level dielectric layers from the first level in a second direction opposite the first direction, with the global bit line electrically coupled to the local sense amplifier.

    Memory cell with improved write margin
    33.
    发明授权
    Memory cell with improved write margin 有权

    公开(公告)号：US09978447B2

    公开(公告)日：2018-05-22

    申请号：US15496655

    申请日：2017-04-25

    Applicant: Intel Corporation

    Inventor： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

    IPC: G11C11/419 ,  G11C11/413 ,  G11C11/417 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

    Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

    Vertical multi-gate thin film transistors
    36.
    发明授权
    Vertical multi-gate thin film transistors 有权

    公开(公告)号：US11862729B2

    公开(公告)日：2024-01-02

    申请号：US17584260

    申请日：2022-01-25

    Applicant: Intel Corporation

    Inventor： Yih Wang ,  Abhishek Sharma ,  Sean Ma ,  Van H. Le

    IPC: H01L29/786 ,  H01L29/66 ,  H10B12/00

    CPC classification number: H01L29/78642 ,  H01L29/66742 ,  H10B12/053 ,  H10B12/34 ,  H10B12/488

    Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

    Replacement metal COB integration process for embedded DRAM
    38.
    发明授权
    Replacement metal COB integration process for embedded DRAM 有权

    公开(公告)号：US11723188B2

    公开(公告)日：2023-08-08

    申请号：US16024578

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Uygar Avci ,  Ian Young ,  Daniel Morris ,  Seiyon Kim ,  Yih Wang ,  Ruth Brain

    IPC: H01L23/522 ,  H01L21/768 ,  H10B12/00 ,  H01L49/02

    CPC classification number: H10B12/315 ,  H01L21/76808 ,  H01L21/76843 ,  H01L23/5226 ,  H01L28/91 ,  H10B12/033 ,  H10B12/50

    Abstract: Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

    VERTICAL MULTI-GATE THIN FILM TRANSISTORS
    40.
    发明申请
    VERTICAL MULTI-GATE THIN FILM TRANSISTORS 有权

    公开(公告)号：US20220149208A1

    公开(公告)日：2022-05-12

    申请号：US17584260

    申请日：2022-01-25

    Applicant: Intel Corporation

    Inventor： Yih Wang ,  Abhishek Sharma ,  Sean Ma ,  Van H. Le

    IPC: H01L29/786 ,  H01L27/108 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66

    Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

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