公开(公告)号：US20210043555A1

公开(公告)日：2021-02-11

申请号：US16944303

申请日：2020-07-31

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Thomas Basler ,  Reinhold Bayerer ,  Ivan Nikitin

IPC: H01L23/498 ,  H01L23/66 ,  H01L23/29 ,  H01L21/56 ,  H01L21/48

Abstract: An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.

公开(公告)号：US20200183056A1

公开(公告)日：2020-06-11

申请号：US16704873

申请日：2019-12-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Dirk Ahlers ,  Andreas Grassmann ,  Andre Uhlemann

IPC: G02B1/118 ,  H05K3/40

Abstract: A power semiconductor module includes a first substrate, wherein the first substrate includes aluminum, a first aluminum oxide layer arranged on the first substrate, a conductive layer arranged on the first aluminum oxide layer, a first semiconductor chip, wherein the first semiconductor chip is arranged on the conductive layer and is electrically connected thereto, and an electrical insulation material enclosing the first semiconductor chip, wherein the first aluminum oxide layer is configured to electrically insulate the first semiconductor chip from the first substrate.

公开(公告)号：US10461017B2

公开(公告)日：2019-10-29

申请号：US15665574

申请日：2017-08-01

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Wolfram Hable ,  Juergen Hoegerl ,  Ivan Nikitin ,  Achim Strass

IPC: H01L23/473 ,  B60R16/02 ,  H01L21/56 ,  H01L23/31 ,  H01L23/433 ,  H01L23/46 ,  H01L21/48 ,  H01L23/373 ,  H01L23/42 ,  H01L23/00 ,  H01L25/07

Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.

公开(公告)号：US20190103378A1

公开(公告)日：2019-04-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US09530752B2

公开(公告)日：2016-12-27

申请号：US14076976

申请日：2013-11-11

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Petteri Palm ,  Joachim Mahler

IPC: H05K13/02 ,  H01L23/00

CPC classification number: H01L24/97 ,  H01L24/24 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A method which comprises arranging a plurality of electronic chips in a plurality of chip accommodation cavities each defined by a respective surface portion of a substrate and a wall delimited by a respective one of a plurality of holes in an electrically conductive frame arranged on the substrate, at least partially encapsulating the electronic chips in the chip accommodation cavities by an encapsulant, and forming electrically conductive contacts for electrically contacting the at least partially encapsulated electronic chips.

Abstract translation: 一种方法，其包括将多个电子芯片布置在由芯片的相应表面部分限定的多个芯片容置空腔中，以及由布置在基板上的导电框架中的多个孔中的相应一个孔限定的壁， 至少部分地通过密封剂将所述电子芯片封装在所述芯片容纳腔中，以及形成用于电接触所述至少部分封装的电子芯片的导电触点。

公开(公告)号：US09385107B2

公开(公告)日：2016-07-05

申请号：US13959712

申请日：2013-08-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/48 ,  H01L25/07 ,  H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/074 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49827 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/08168 ,  H01L2224/32225 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/40101 ,  H01L2224/40137 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: A device includes a substrate including an electrically insulating core, a first electrically conductive material arranged over a first main surface of the substrate, and a second electrically conductive material arranged over a second main surface of the substrate opposite to the first main surface. The device further includes an electrically conductive connection extending from the first main surface to the second main surface and electrically coupling the first electrically conductive material and the second electrically conductive material, a first semiconductor chip arranged over the first main surface and electrically coupled to the first electrically conductive material, and a second semiconductor chip arranged over the second main surface and electrically coupled to the second electrically conductive material.

Abstract translation: 一种器件包括：衬底，其包括电绝缘芯，布置在衬底的第一主表面上的第一导电材料和布置在与第一主表面相对的衬底的第二主表面上的第二导电材料。 该装置还包括从第一主表面延伸到第二主表面并且电耦合第一导电材料和第二导电材料的导电连接，第一半导体芯片，布置在第一主表面上并电耦合到第一导电材料 导电材料和布置在第二主表面上并电耦合到第二导电材料的第二半导体芯片。

公开(公告)号：US20250062290A1

公开(公告)日：2025-02-20

申请号：US18934846

申请日：2024-11-01

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bãßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498

Abstract: A power semiconductor package includes a plurality of first power semiconductor dies attached to a first metallization layer and a plurality of second power semiconductor dies attached to a second metallization layer. A first structured metal frame disposed above the first metallization layer is electrically connected to a load terminal of each first power semiconductor die. A second structured metal frame disposed above the second metallization layer is electrically connected to a load terminal of each second power semiconductor die and to the first metallization layer. A first lead is electrically connected to the second metallization layer. A second lead is electrically connected to the second metallization layer. A third lead interposed between the first and second leads is electrically connected to the first structured metal frame. A fourth lead is electrically connected to the second structured metal frame.

公开(公告)号：US20230170316A1

公开(公告)日：2023-06-01

申请号：US17537822

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Adrian Lis ,  Peter Scherl ,  Achim Althaus

IPC: H01L23/00 ,  H05K1/11 ,  H01L23/498

CPC classification number: H01L24/05 ,  H05K1/11 ,  H01L24/04 ,  H01L23/49838 ,  H01L24/40 ,  H01L2224/04034 ,  H01L2224/05556 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L24/06 ,  H01L2224/40475 ,  H01L23/49811 ,  H05K1/18

Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

公开(公告)号：US20220115293A1

公开(公告)日：2022-04-14

申请号：US17557168

申请日：2021-12-21

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Wolfram Hable ,  Juergen Hoegerl ,  Ivan Nikitin ,  Achim Strass

IPC: H01L23/42 ,  H01L23/495 ,  H01L23/552 ,  H01L23/373 ,  H01L23/473

Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.

公开(公告)号：US11244886B2

公开(公告)日：2022-02-08

申请号：US15710852

申请日：2017-09-21

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Wolfram Hable ,  Juergen Hoegerl ,  Ivan Nikitin ,  Achim Strass

IPC: H01L23/42 ,  H01L23/495 ,  H01L23/552 ,  H01L23/373 ,  H01L23/473 ,  H01L23/00 ,  H01L23/31

Abstract: A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.