公开(公告)号：US20230197800A1

公开(公告)日：2023-06-22

申请号：US17556737

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Cheng-Ying Huang ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Patrick Morrow ,  Ashish Agrawal ,  Willy Rachmady ,  Nazila Haratipour ,  Seung Hoon Sung

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/40 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/401 ,  H01L29/0665 ,  H01L27/0922 ,  H01L29/66742

Abstract: Techniques are provided herein to form semiconductor devices having a non-reactive metal contact in an epi region of a stacked transistor configuration. An n-channel device may be located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A deep and narrow contact may be formed from either the frontside or the backside of the integrated circuit through the stacked source or drain regions. According to some embodiments, the contact is formed using a refractory metal or other non-reactive metal such that no silicide or germanide is formed with the epi material of the source or drain regions at the boundary between the contact and the source or drain regions.

公开(公告)号：US20230197777A1

公开(公告)日：2023-06-22

申请号：US17556748

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Cheng-Ying Huang ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Patrick Morrow ,  Ashish Agrawal ,  Willy Rachmady ,  Nazila Haratipour ,  Seung Hoon Sung ,  I-Cheng Tung ,  Christopher M. Neumann ,  Koustav Ganguly ,  Subrina Rafique

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices utilizing a metal fill in an epi region of a stacked transistor configuration. In one example, an n-channel device and the p-channel device may both be GAA transistors each having any number of nanoribbons extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. A metal fill may be provided around the source or drain region of the bottom semiconductor device to provide a high contact area between the highly conductive metal fill and the epitaxial material of that source or drain region. Metal fill may also be used around the top source or drain region to further improve conductivity throughout both of the stacked source or drain regions.

公开(公告)号：US20230089395A1

公开(公告)日：2023-03-23

申请号：US17448373

申请日：2021-09-22

Applicant: INTEL CORPORATION

Inventor： Benjamin Orr ,  Nicholas A. Thomson ,  Ayan Kar ,  Nathan D. Jack ,  Kalyan C. Kolluru ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

公开(公告)号：US11569238B2

公开(公告)日：2023-01-31

申请号：US16222940

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Kimin Jun ,  Hui Jae Yoo ,  Patrick Morrow ,  Sean T. Ma ,  Ahn Phan ,  Abhishek Sharma ,  Cheng-Ying Huang ,  Ehren Mannebach

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L23/528 ,  H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L29/417 ,  H01L29/51

Abstract: Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US11552104B2

公开(公告)日：2023-01-10

申请号：US16279693

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow ,  Kimin Jun

IPC: H01L27/12 ,  H01L21/84

Abstract: Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.

公开(公告)号：US11482621B2

公开(公告)日：2022-10-25

申请号：US16143222

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Patrick Morrow ,  Aaron Lilak ,  Rishabh Mehandru ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Kimin Jun ,  Ryan Keech ,  Anh Phan ,  Ehren Mannebach

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06

Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.

公开(公告)号：US20220328663A1

公开(公告)日：2022-10-13

申请号：US17853036

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Jack T. Kavalieros ,  Ian A. Young

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.

公开(公告)号：US11380684B2

公开(公告)日：2022-07-05

申请号：US16145817

申请日：2018-09-28

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Aaron Lilak ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Willy Rachmady ,  Anh Phan ,  Ehren Mannebach ,  Abhishek Sharma ,  Patrick Morrow ,  Hui Jae Yoo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.

公开(公告)号：US11296203B2

公开(公告)日：2022-04-05

申请号：US16649183

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey

IPC: H01L29/51 ,  H01L21/285 ,  H01L23/16 ,  H01L23/367 ,  H01L23/00 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment includes a system comprising: a switching device that includes a fin; and a source contact on a source, a gate contact on a channel, and a drain contact on a drain; wherein the gate contact includes: (a)(i) a first layer that includes oxygen, the first layer directly contacting the fin, (a)(ii) a second layer that includes a dielectric material, (c) a third layer that includes at least one of aluminum, titanium, ruthenium, zirconium, hafnium, tantalum, niobium, vanadium, thorium, barium, magnesium, cerium, and lanthanum, and (a)(iii) a fourth layer that includes a metal, wherein (b)(i) the source contact, the gate contact, and the drain contact are all on the fin, and (b)(ii) the second layer is between the first and fourth layers. Other embodiments are described herein.

公开(公告)号：US11244943B2

公开(公告)日：2022-02-08

申请号：US16728983

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.