-
公开(公告)号：CA2465014A1
公开(公告)日：2005-04-29
申请号：CA2465014
申请日：2004-04-19
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , SEO JAE-HYUN , LEE YONG-TAE , LEE SOO-IN , KIM SEUNG-WON
Abstract: Provided is a modulation apparatus that can reduce time delay of on-channel repeaters in a terrestrial digital television broadcasting system. The time delay is caused by a filter during the modulation operation in the on-channel repeaters. The modulation apparatus of the present research includes: a baseband signal forming unit for forming a baseband signal by combining the output signals of an equalization unit with the pre-defined field/segment synchronization signals in the on-channel repeaters; a pilot inserting unit for inserting a pilot signal to the baseband signal; an up-sampling unit for up-sampling the baseband signal with the pilot signal; a VSB filtering unit for filtering the up-sampled baseband signal based on a Window technique and/or an Equi-Ripple filter to thereby form an in- phase (I) signal and a quadrature (Q) signal; an up-converting unit for up-converting the frequencies of the filtered I and Q signals to frequencies of an intermediate frequency (IF) band; an adding unit for adding the up-converted L and Q signals and converting a resultant signal into a digital VSB signal of the IF band; and a digital-to-analogue converting unit for converting the digital signal of the IF band to an analogue signal.
-
公开(公告)号：CA2864718A1
公开(公告)日：2016-02-14
申请号：CA2864718
申请日：2014-09-25
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KIM HEUNG-MOOK , KWON SUN-HYOUNG , HUR NAM-HO
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
-
公开(公告)号：CA2864694A1
公开(公告)日：2016-02-14
申请号：CA2864694
申请日：2014-09-25
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KWON SUN-HYOUNG , HUR NAM-HO , KIM HEUNG-MOOK
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
-
公开(公告)号：CA2892103A1
公开(公告)日：2015-11-22
申请号：CA2892103
申请日：2015-05-21
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KWON SUN-HYOUNG , LIM BO-MI , LEE JAE-YOUNG , KIM HEUNG-MOOK , HUR NAM-HO
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
-
公开(公告)号：MX2015001936A
公开(公告)日：2015-10-26
申请号：MX2015001936
申请日：2015-02-12
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KIM HEUNG-MOOK , KWON SUN-HYOUNG , HUR NAM-HO , LEE JAE-YOUNG
IPC: H04N19/36
Abstract: Se divulgan un modulador y un método de modulación que usan una constelación de señal de 16 símbolos no uniforme; el modulador incluye una memoria y un procesador; la memoria recibe una palabra código que corresponde con un código de verificación de paridad de baja densidad (LDPC) que tiene una tasa de código de 7/15; el procesador mapea la palabra código a 16 símbolos de la constelación de señal de 16 símbolos no uniforme sobre una base de 4 bits.
-
Patent Agency Ranking
公开(公告)号：MX2014012121A
公开(公告)日：2015-08-19
申请号：MX2014012121
申请日：2014-10-07
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KIM HEUNG-MOOK , KWON SUN-HYOUNG , HUR NAM-HO
Abstract: Se describe un codificador de revisión de paridad de baja densidad (LDPC), un decodificador de LDPC y un método codificador de LDPC; el codificador de LDPC incluye una primera memoria, una segunda memoria y un procesador; la primera memoria almacena una palabra código de LDPC que tiene una longitud de 64800 y un índice de código de 7/15; la segunda memoria es inicializada a 0; el procesador genera la palabra código de LDPC que corresponde a los bits de información al realizar acumulación con respecto a la segunda memoria al usar una secuencia que corresponde a una matriz de revisión de paridad (PCM).
-
公开(公告)号：CA2881540A1
公开(公告)日：2015-08-13
申请号：CA2881540
申请日：2015-02-11
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KWON SUN-HYOUNG , LEE JAE-YOUNG , KIM HEUNG-MOOK , HUR NAM-HO
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
-
公开(公告)号：CA2881538A1
公开(公告)日：2015-08-13
申请号：CA2881538
申请日：2015-02-11
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , KWON SUN-HYOUNG , LEE JAE-YOUNG , KIM HEUNG-MOOK , HUR NAM-HO
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
-
公开(公告)号：CA2553753C
公开(公告)日：2013-06-04
申请号：CA2553753
申请日：2004-12-31
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： PARK SUNG-IK , LEE YONG-TAE , EUM HO-MIN , KIM HEUNG-MOOK , SEO JAE-HYUN , KIM SEUNG-WON , LEE SOO-IN
Abstract: Provided is a modulating apparatus and method of an on-channel repeater. An object of the present invention is to provide a modulating apparatus of an on-channel repeater for reducing time delay by configuring and up-sampling a baseband signal, filtering the up-sampled baseband signal with an Equi-Ripple (ER) filter or in a window method, and converting the filtered baseband signal into an RF signal. The modulating apparatus includes: a baseband signal configuring unit for configuring a baseband. signal by combining an input field and a segment sync signal; a pilot adding unit for adding a pilot signal to the baseband signal; a filtering unit for filtering the baseband signal with the pilot signal; and an RF up-converting unit for up-converting the filtered signal into an RF signal. The present invention is used to form an on-channel repeating network in a transmitting system including a digital TV broadcasting system.
-
公开(公告)号：CA2564236C
公开(公告)日：2013-04-02
申请号：CA2564236
申请日：2004-12-31
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： SEO JAE-HYUN , LEE YONG-TAE , KIM HEUNG-MOOK , EUM HO-MIN , PARK SUNG-IK , KIM SEUNG-WON , LEE SOO-IN
Abstract: Provided are an on-channel repeater and a method thereof. The repeater receives signals on one channel and distributes the signals on the same channel by converting RF signals from a main transmitter into baseband signals; equalizing them in a high-performance equalizer; adding a repeater identifier to them; modulating the baseband signals with the repeater identifier into RF signals. The repeater includes: a receiver for receiving RF signals; a demodulator for demodulating the RF signals into baseband signals; an equalizer for equalizing the baseband signals; an adder for adding a repeater identifier to the baseband signals; a modulator for modulating the baseband signals with the repeater identifier added in the adder into RF signals; and a transmitter for transmitting the RF signals modulated in the modulator. The technology of the present invention is used to form an on-channel repeating network in an arbitrary transmission system including a digital television broadcasting system.
-
-
-
-
-
-
-
-
-
Search Results
91
records
(took 0.023 seconds)
