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公开(公告)号：DE60131027D1
公开(公告)日：2007-11-29
申请号：DE60131027
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.
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公开(公告)号：DE60124147T2
公开(公告)日：2007-09-06
申请号：DE60124147
申请日：2001-09-18
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH
IPC: H03M3/02
Abstract: A bandpass SIGMADELTA ADC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, a two-path interleaved resonator, or a four-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMADELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMADELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMADELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.
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公开(公告)号：AT343871T
公开(公告)日：2006-11-15
申请号：AT01973125
申请日：2001-09-18
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH
IPC: H03M3/02
Abstract: A bandpass SIGMADELTA ADC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, a two-path interleaved resonator, or a four-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMADELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMADELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMADELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.
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公开(公告)号：MY122792A
公开(公告)日：2006-05-31
申请号：MYPI20020686
申请日：2002-02-27
Applicant: QUALCOMM INC
Inventor： ZHANG HAITAO , BAZARJANI SEYFOLLAH , ZOU QIUZHEN , JHA SANJAY
IPC: H01L23/24 , H01L25/18 , H01L23/31 , H01L25/065 , H01L25/07
Abstract: TECHNIQUES FOR FABRICATING ANALOG AND DIGITAL CIRCUITS ON SEPARATE DIES AND STACKING AND INTEGRATING THE DIES WITHIN A SINGLE PACKAGE TO FORM A MIXED-SIGNAL IC THAT PROVIDESMANY BENEFITS. IN ONE ASPECT, THE ANALOG AND DIGITAL CIRCUITS ARE IMPLEMENTED ON TWO SEPARATE DIES 120, 130) USING POSSIBLY DIFFERENT IC PROCESSES SUITABLE FOR THESE DIFFERENT TYPES OF CIRCUITS. THE ANALOG AND DIGITAL DIES (120, 130) ARE THEREAFTER INTEGRATED (STACKED) AND ENCAPSULATED WITHIN THE SINGLE PACKAGE. BONDING PADS (120, 130) ARE PROVIDED TO INTERCONNECT THE DIES AND ENCAPSULATED WITHIN THE SINGLE PACKAGE . BONDING PADS (122, 132) ARE PROVIDED TO INTERCONNECT THE DIES AND TO CONNECT THE DIES TO EXTERNAL PINS .THE BONDING PADS MAY BE LOCATED AND ARRANGED IN A MANNER TO PROVIDETHE REQUIRED CONNECTIVITY WHILE MINIMIZING THE AMOUNT OF DIE AREA REQUIRED TO IMPLEMENT THE PADS. IN ANOTHER ASPECT, THE DIE-TO-DIE CONNECTIVITY MAY BE TESTED IN CONJUNCTION WITH A SERIAL BUS INTERFACE . FIGURE 3B, 3C, 4B
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公开(公告)号：BR0115060A
公开(公告)日：2005-10-18
申请号：BR0115060
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.
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Patent Agency Ranking
公开(公告)号：BR0206834A
公开(公告)日：2004-12-28
申请号：BR0206834
申请日：2002-01-30
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , GOLDBLATT JEREMY
Abstract: A bias circuit is described for use in biasing an operational amplifier to maintain a constant transconductance divided by load capacitance (i.e. a constant gm/CL) despite temperature and process variations and despite body effects. In one example, the bias circuit includes a pair of current source devices and a switched capacitor (SC) equivalent resistor circuit for developing an equivalent resistance between the current source devices. The equivalent resistor circuit includes a sampling capacitor. First and second clock inputs are connected to the capacitor providing non-overlapping clock signals at a predetermined sampling frequency to establish a resistance equivalent. By providing an SC equivalent resistor circuit clocked by non-overlapping fixed clock signals, the gm/CL of the bias circuit is maintained substantially constant. Hence, a fixed bandwidth is maintained within the operational amplifier being biased. When employed in connection with operational amplifiers of an SC circuit, the constant bandwidth enables the SC circuit to operate at a constant switching speed despite temp and process variations. Furthermore, by positioning the resistance equivalent circuit between the current source devices of the bias circuit, voltage differentials between the sources are eliminated thereby removing any threshold voltage mismatch and thus compensating for body effect variations. Other bias circuit examples are also described including a stray insensitive bias circuit and a bias circuit employing three mutually non-overlapping clock signals.
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公开(公告)号：BR0207798A
公开(公告)日：2004-07-06
申请号：BR0207798
申请日：2002-02-22
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , ZHANG HAITAO , ZOU QUIZHEN , JHA SANJAY
IPC: H01L25/18 , H01L23/31 , H01L25/065 , H01L25/07
Abstract: Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.
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公开(公告)号：AU2003280465A1
公开(公告)日：2004-01-19
申请号：AU2003280465
申请日：2003-06-26
Applicant: QUALCOMM INC
Inventor： KEEHR EDWARD , WANG SEAN , BAZARJANI SEYFOLLAH
Abstract: A digital to analog converter augmented with Direct Charge Transfer (DCT) techniques. A digital to analog converter augmented with DCT and CDS techniques. A digital to analog converter augmented with Postfilter Droop Compensation.
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公开(公告)号：AU2002235510A1
公开(公告)日：2002-08-28
申请号：AU2002235510
申请日：2002-01-30
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH
Abstract: A multi-stage circuit that includes a number of stages, with at least one stage being of a first type and at least one stage being of a second type. Each stage receives either a circuit input signal or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each first type (or second type) stage operates based on one or more clock signals having a frequency of fS (or fS/N), where fS is the sampling frequency and N is an integer greater than one. Each first type stage may be implemented with a correlated double-sampling circuit, an auto-zeroing circuit, or a chopper stabilization circuit. Each second type stage may be implemented with a multi-sampling (i.e., double-sampling or higher order sampling) circuit. The multi-stage circuit may be designed to implement a lowpass filter, a DELTASIGMA ADC, or some other circuit.
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公开(公告)号：AU9273501A
公开(公告)日：2002-03-26
申请号：AU9273501
申请日：2001-09-18
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH
IPC: H03M3/02
Abstract: A bandpass SIGMADELTA ADC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, a two-path interleaved resonator, or a four-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMADELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMADELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMADELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.
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