33.
    发明专利
    未知

    公开(公告)号:DE60136092D1

    公开(公告)日:2008-11-20

    申请号:DE60136092

    申请日:2001-11-20

    Applicant: QUALCOMM INC

    Abstract: A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer, the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

    MULTIPATH SEARCH PROCESSOR FOR A SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM

    公开(公告)号:MY120873A

    公开(公告)日:2005-12-30

    申请号:MYPI9502749

    申请日:1995-09-18

    Applicant: QUALCOMM INC

    Abstract: AN INTEGRATED SEARCH PROCESSOR (128) USED IN A MODEM FOR A SPREAD SPECTRUM COMMUNICATIONS SYSTEM BUFFERS RECEIVE SAMPLES AND UTILIZES A TIME SLICED TRANSFORM PROCESSOR (120) OPERATING ON SUCCESSIVE OFFSETS FROM THE BUFFER. THE SEARCH PROCESSOR (128) AUTONOMOUSLY STEPS THROUGH A SEARCH AS CONFIGURED BY A MICROPROCESSOR SPECIFIED SEARCH PARAMETER SET, WHICH CAN INCLUDE THE GROUP OF ANTENNAS TO SEARCH OVER, THE STARTING OFFSET AND WIDTH OF THE SEARCH WINDOW TO SEARCH OVER, AND THE NUMBER OF WALSH SYMBOLS TO ACCUMULATE RESULTS AT EACH OFFSET. THE SEARCH PROCESSOR (128) CALCULATES THE CORRELATION ENERGY AT EACH OFFSET, AND PRESENTS A SUMMARY REPORT OF THE BEST PATHS FOUND IN THE SEARCH TO USE FOR DEMODULATION ELEMENT REASSIGNMENT. THIS REDUCES THE SEARCHING PROCESS RELATED WORKLOAD OF THE MICROPROCESSOR (136) AND ALSO REDUCES THE MODEM COSTS BY ALLOWING A COMPLETE CHANNEL ELEMENT MODEM CIRCUIT (110) TO BE PRODUCED IN A SINGLE IC.

    36.
    发明专利
    未知

    公开(公告)号:FI113820B

    公开(公告)日:2004-06-15

    申请号:FI974132

    申请日:1997-11-04

    Applicant: QUALCOMM INC

    Abstract: An integrated search processor used in a modem for a spread spectrum communications system buffers receive samples and utilizes a time sliced transform processor operating on successive offsets from the buffer. The search processor autonomously steps through a search as configured by a microprocessor specified search parameter set, which can include the group of antennas to search over, the starting offset and width of the search window to search over, and the number of Walsh symbols to accumulate results at each offset. The search processor calculates the correlation energy at each offset, and presents a summary report of the best paths found in the search to use for demodulation element reassignment. The search is done in a linear fashion independent of the probability that a signal being searched for was transmitted at any given time.

    METODO Y APARATO PARA PROCESAR UNA SENAL RECIBIDA EN UN SISTEMA DE.

    公开(公告)号:MXPA03004636A

    公开(公告)日:2004-04-20

    申请号:MXPA03004636

    申请日:2001-11-20

    Applicant: QUALCOMM INC

    Inventor: EASTON KENNETH D

    Abstract: Una unidad receptora incluye una primera memoria intermedia que recibe y almacena muestras digitalizadas en un indice de muestra particular y un procesador de datos que recupera segmentos de las muestras digitalizadas de la primera memoria intermedia y procesa los segmentos recuperados con un conjunto particular de valores de parametro. El procesador de datos es operado basado en un reloj de procesamiento que tiene una frecuencia que es (por ejemplo, diez o mas veces mas alto) que el indice de la muestra. Los casos multiples de senales recibidas pueden ser procesados recuperando y procesando segmentos multiples de la muestras digitalizadas de la primera memoria Intermedia, la unidad receptora generalmente incluye ademas un receptor que recibe y procesa una senal transmitida para proporcionar muestras digitalizadas y un controlador que despacha tareas para el procesador de datos. El procesador de datos puede ser disenado para incluir un correlacionador, una desmodulacion de simbolos y combinador, un primer acumulador, una segunda memoria intermedia o una combinacion de los mismos. El correlacionador desdifunde los segmentos recuperados de las muestras digitalizadas con segmentos correspondientes de las secuencias de desdifusion PN para proporcionar muestras correlacionadas, las cuales son procesadas adicionalmente por el desmodulador de simbolo y combinador para proporcionar simbolos procesados. La segunda memoria intermedia almacena los simbolos procesados, y puede estar disenada para proporcionar la desintercalacion de los simbolos procesados.

    MOBILE DEMODULATOR ARCHITECTURE FOR A SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM

    公开(公告)号:MY115194A

    公开(公告)日:2003-04-30

    申请号:MYPI9602426

    申请日:1996-06-14

    Applicant: QUALCOMM INC

    Inventor: EASTON KENNETH D

    Abstract: THE PRESENT INVENTION INVOLVES DEMODULATING A SIGNAL IN A SPREAD SPECTRUM MULTIPLE ACCESS SYSTEM EMPLOYING A PILOT ON THE FORWARD LINK. THE RAKE RECEIVER SEPARATES THE SIGNAL PROCESSING BASED ON THE PERIOD OVER WHICH THE PROCESSING OCCURS. SYMBOL RATE PROCESSING IS PERFORMED BY A SINGLE TIME-SHARED MULTIPLY-ACCUMULATE DATAPATH THAT SERVICES MULTIPLE FINGER FRONT ENDS AND A SEARCHER FRONT END. THE FRONT ENDS ARE DEDICATED CIRCUITS THAT PERFORM ALL CHIP RATE PROCESSING, PRODUCING A DATA VECTOR AND ASSERTING A FLAG INDICATING THE RESULTS ARE READY TO BE SERVICED BY THE SHARED DATAPATH. A DATAPATH CONTROLLER ARBITRATES USE OF THE DATAPATH BETWEEN THE FINGER FRONT ENDS, THE SEARCHER FRONT END, AND COMBINING FUNCTIONS, CONFIGURING THE DATAPATH TO SERVICE THEM ON A FIRST-COME, FIRST-SERVE BASIS. THE CONTROLLER SEQUENCES THE DATAPATH THROUGH A FIXED ROUTINE AS DICTATED BY THE SIGNAL PRICESSING ASSOCIATED WITH THE BLOCK BEING SERVICED. (FIG.6)

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