公开(公告)号：HK1063541A1

公开(公告)日：2004-12-31

申请号：HK04106242

申请日：2004-08-20

Applicant: QUALCOMM INC

Inventor： EASTON KENNETH D ,  BLACK PETER J

IPC: H04B1/707 ,  H04B1/709 ,  H04B1/7093 ,  H04Q7/38

Abstract: A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer, the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

公开(公告)号：AT237203T

公开(公告)日：2003-04-15

申请号：AT96902671

申请日：1996-01-16

Applicant: QUALCOMM INC

Inventor： LEVIN JEFFREY A ,  WERNER DAVID E ,  EASTON KENNETH D

IPC: H04B7/216 ,  H04B7/26 ,  H04L27/30 ,  H04W88/08

公开(公告)号：HK1015199A1

公开(公告)日：1999-10-08

申请号：HK98116186

申请日：1998-12-28

Applicant: QUALCOMM INC

Inventor： LEVIN JEFFREY A ,  WERNER DAVID E ,  EASTON KENNETH D

IPC: H04B7/216 ,  H04B7/26 ,  H04L27/30 ,  H04W88/08 ,  H04B

公开(公告)号：HK1010956A1

公开(公告)日：1999-07-02

申请号：HK98110021

申请日：1998-08-19

Applicant: QUALCOMM INC

Inventor： EASTON KENNETH D

IPC: H04B1/7115 ,  H04B1/7117

Abstract: The present invention involves demodulating a signal in a spread spectrum multiple access system employing a pilot on the forward link. The rake receiver separates the signal processing based on the period over which the processing occurs. Symbol rate processing is performed by a single time-shared multiply-accumulate datapath that services multiple finger front ends and a searcher front end. The front ends are dedicated circuits that perform all chip rate processing, producing a data vector and asserting a flag indicating the results are ready to be serviced by the shared datapath. A datapath controller arbitrates use of the datapath between the finger front ends, the searcher front end, and combining functions, configuring the datapath to service them on a first-come, first-serve basis. The controller sequences the datapath through a fixed routine as dictated by the signal processing associated with the block being serviced.

公开(公告)号：BR9609173A

公开(公告)日：1999-05-04

申请号：BR9609173

申请日：1996-06-18

Applicant: QUALCOMM INC

Inventor： EASTON KENNETH D

IPC: H04B1/7115 ,  H04B1/7117 ,  H04B7/26

Abstract: The present invention involves demodulating a signal in a spread spectrum multiple access system employing a pilot on the forward link. The rake receiver separates the signal processing based on the period over which the processing occurs. Symbol rate processing is performed by a single time-shared multiply-accumulate datapath that services multiple finger front ends and a searcher front end. The front ends are dedicated circuits that perform all chip rate processing, producing a data vector and asserting a flag indicating the results are ready to be serviced by the shared datapath. A datapath controller arbitrates use of the datapath between the finger front ends, the searcher front end, and combining functions, configuring the datapath to service them on a first-come, first-serve basis. The controller sequences the datapath through a fixed routine as dictated by the signal processing associated with the block being serviced.

公开(公告)号：AU9030298A

公开(公告)日：1999-03-16

申请号：AU9030298

申请日：1998-08-24

Applicant: QUALCOMM INC

Inventor： EASTON KENNETH D

IPC: G06F17/14

Abstract: A variable block size 2-D IDCT engine (10) which can compute any arbitrary mix of transforms. A first 1-D IDCT processor (20a) computes the transform of the data block by columns and stores the intermediate results in a transposition memory. A second 1-D IDCT processor (20b) computes the transform of the intermediate results by rows. Different mix of transforms can be easily performed by correctly ordering the input data, selectively combining the input data before the butterfly stages, and controlling the additions and multiplications at each stage of butterfly. The unnecessary butterflies are placed in the bypass mode. The butterflies can be implemented with serial adders (56) and bit-serial multipliers to greatly simplify the hardware design and minimize the routing requirements between successive stages of butterfly. The fully pipelined structure allows the IDCT engine to maintain a throughput rate of one pixel per clock cycle.

公开(公告)号：ZA975595B

公开(公告)日：1998-10-08

申请号：ZA975595

申请日：1997-06-24

Applicant: QUALCOMM INC

Inventor： EASTON KENNETH D ,  BLACK PETER J

IPC: H03H17/06 ,  H03H ,  H01P ,  H04M

公开(公告)号：AR002539A1

公开(公告)日：1998-03-25

申请号：AR10323896

申请日：1996-06-20

Applicant: QUALCOMM INC

Inventor： EASTON KENNETH D

IPC: H04B1/707 ,  H04B1/7115 ,  H04B1/7117 ,  H04J13/02

Abstract: La invención se refiere a un aparato mejorado para demodulación de una senal en una disposición de comunicación celular, de espectro distribuido y demúltiple acceso; y a un método para demodulación de dicha senal que utiliza dicho aparato.D e acuerdo a la invención se separa el procesamiento de la senalen base al período durante el cual tiene lugar el procesamiento. El procesamiento de la velocidad de los símbolos es llevado a cabo por unatrayectoria de datos simple detiemp o compartido y de multiplicar-acumular que sirve a múltiples extremidades frontales de dedos y a una extremidad frontaldel explorador. Las extremidades frontales son circuitos dedicados que llevan a cabo todo el procesamiento de lavelocidad de lo s chips, obteniéndose unvector de datos y afirmándose una bandera que indica que los resultados están listos para ser servidos por una trayectoria de datos compartida. Uncontrolador de trayectorias de datos, arbitra la utilizaciónde la trayectoria de datos entre las extremidades frontales de los dedos, la extremidad frontalexploradora, y las funciones de combinación, configurando la trayectoria de datos para servirlos en una base de el primero en llegar, será el primeroenser servido. El controlador secuencia la trayectoria de datos por intermedio de una rutina fija dictada por el procesamiento de las senales asociada con losbloques que están siendo servidos. La invención también propone un método parademodulación de dichas senal es basado en la estructura de dicho aparato.

公开(公告)号：FI962258A

公开(公告)日：1996-07-22

申请号：FI962258

申请日：1996-05-29

Applicant: QUALCOMM INC

Inventor： EASTON KENNETH D ,  LEVIN JEFFREY A

IPC: H04L1/02 ,  H04B1/707 ,  H04B7/26 ,  H04J11/00 ,  H04J13/00 ,  H04L27/30 ,  H04Q7/20 ,  H04B

Abstract: An integrated search processor used in a modem for a spread spectrum communications system buffers receive samples and utilizes a time sliced transform processor operating on successive offsets from the buffer. The search processor autonomously steps through a search as configured by a microprocessor specified search parameter set, which can include the group of antennas to search over, the starting offset and width of the search window to search over, and the number of Walsh symbols to accumulate results at each offset. The search processor calculates the correlation energy at each offset, and presents a summary report of the best paths found in the search to use for demodulation element reassignment. This reduces the searching process related workload of the microprocessor and also reduces the modem costs by allowing a complete channel element modem circuit to be produced in a single IC.

公开(公告)号：WO0133870A3

公开(公告)日：2001-11-22

申请号：PCT/US0030387

申请日：2000-11-03

Applicant: QUALCOMM INC

Inventor： YU NICHOLAS K ,  EASTON KENNETH D ,  SANKURATRI RAGHU

IPC: H03L7/00 ,  H04B1/16 ,  H04B7/26 ,  H04M1/73 ,  H04W52/02 ,  H04Q7/32

CPC classification number: H04W52/0293 ,  H04W52/029 ,  Y02D70/00 ,  Y02D70/12 ,  Y02D70/122

Abstract: A technique is described for activating an active-mode high frequency clock (102) following a sleep period for use within a mobile station wherein selected components of the mobile station operate using a low power, low frequency sleep-mode clock (104) during the sleep period and the faster high frequency active-mode clock (102) during non-sleep periods. In one embodiment, the technique is implemented by a device having a wake-up estimation unit (108) for estimating a wake up time using the sleep-mode clock (104) and a frequency drift compensation unit for compensating for any error in the estimated wake up time caused by frequency drift in the sleep-mode clock (104). An off-set time compensation unit (112) is also provided for compensating for a lack of precision in the low frequency sleep-mode clock (104) resulting in a possible error in the estimated wake up time. The lack of precision can result in an initial timing off-set error at the beginning of the sleep period and a final timing off-set error at the end of the sleep period. Both the frequency drift compensation unit (110) and the off-set time compensation unit employ a high frequency transition-mode clock signal for use in calculating the time required to adjust the wake-up time. The transition-mode clock (106), which may have the same frequency as the active-mode clock (102), is employed only at the beginning and end of the sleep period and is deactivated throughout most of the sleep period to reduce power consumption.

Abstract translation: 描述了一种用于激活休眠期之后的活动模式高频时钟（102）的技术，用于在移动站期间使用的移动站的选定组件在期间使用低功率，低频睡眠模式时钟（104） 睡眠期间和非睡眠期间更快的高频主动模式时钟（102）。 在一个实施例中，该技术由具有用于使用睡眠模式时钟（104）估计唤醒时间的唤醒估计单元（108）的设备和用于补偿所估计的任何错误的频率漂移补偿单元来实现 由休眠模式时钟（104）中的频率漂移引起的唤醒时间。 还提供了一种偏置时间补偿单元（112），用于补偿低频睡眠模式时钟（104）中的精度不足，从而导致所估计的唤醒时间中的可能误差。 缺乏精度可能导致睡眠周期开始时的初始定时偏移误差和睡眠周期结束时的最终定时偏移误差。 频率漂移补偿单元（110）和偏移时间补偿单元均采用高频转换模式时钟信号，用于计算调节唤醒时间所需的时间。 可以仅在活动模式时钟（102）具有相同频率的转换模式时钟（106）仅在睡眠周期的开始和结束时使用，并且在整个睡眠周期的大部分期间被去激活以减少功耗 。