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    31.
    发明专利
    未知

    公开(公告)号：DE68912979T2

    公开(公告)日：1994-05-19

    申请号：DE68912979

    申请日：1989-06-16

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  PASCUCCI LUIGI ,  VILLA CORRADO

    IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07 ,  G11C5/00 ,  G11C17/00 ,  G11C16/06

    Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

    32.
    发明专利
    未知

    公开(公告)号：DE68912979D1

    公开(公告)日：1994-03-24

    申请号：DE68912979

    申请日：1989-06-16

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  PASCUCCI LUIGI ,  VILLA CORRADO

    IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07 ,  G11C5/00 ,  G11C17/00 ,  G11C16/06

    Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

    36.
    发明专利
    未知

    公开(公告)号：ITVA910026D0

    公开(公告)日：1991-08-30

    申请号：ITVA910026

    申请日：1991-08-30

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G06F1/24 ,  H03K17/00 ,  H03K17/22

    Abstract: A power-on reset circuit utilizes capacitive couplings and does not establish any static current path bewteen the supply rails. The circuit has a null static consumption and may be advantageously integrated in CMOS micrologics. Moreover the circuit is insensitive to rebounds on the supply rails and to internal and external noise.

    38.
    发明专利
    未知

    公开(公告)号：IT1228822B

    公开(公告)日：1991-07-04

    申请号：IT1987589

    申请日：1989-03-23

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  RIVA CARLO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C

    Abstract: A reference cell for reading EEPROM memory devices, capable of discharging any charges present in its own floating gate (3) without varying the geometry of the cell with respect to that of the associated memory cells and without requiring specific manufacturing steps. For this purpose, a switch element, for example a diode (D1), is provided between the floating gate (3) and the substrate (11) of the device and discharges any charges present in the floating gate toward the substrate during the cell idle state (in the absence of read signals)

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