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    2.
    发明专利
    未知

    公开(公告)号：DE69125119T2

    公开(公告)日：1997-09-25

    申请号：DE69125119

    申请日：1991-12-18

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： DALLABORA MARCO ,  VILLA CORRADO

    IPC: G11C16/06 ,  G11C17/00 ,  G11C16/28

    Abstract: A memory cell reading circuit has a reference cell bit line and a matrix cell bit line connected to a supply voltage through respective loads and furthermore connected by normally-off equalization transistors which are enabled by a first clock signal. The bit lines are further connected by normally-off resistive equalization transistors whose resistance is significant in conducting conditions. The equalization transistors are enabled by a first clock signal and the resistive equalization transistor are enabled by a second clock signal which has a duration that extends longer than the first clock signal. The memory cell reading circuit decreases the "read" time required for a memory cell, as compared to reading circuits previously used.

    4.
    发明专利
    未知

    公开(公告)号：IT8883645D0

    公开(公告)日：1988-06-28

    申请号：IT8364588

    申请日：1988-06-28

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  PASCUCCI LUIGI ,  VILLA CORRADO

    IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

    Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

    8.
    发明专利
    未知

    公开(公告)号：IT1246754B

    公开(公告)日：1994-11-26

    申请号：IT2256890

    申请日：1990-12-28

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： DALLABORA MARCO ,  VILLA CORRADO

    IPC: G11C16/06 ,  G11C17/00 ,  G11C16/28 ,  G11C

    Abstract: A memory cell reading circuit has a reference cell bit line and a matrix cell bit line connected to a supply voltage through respective loads and furthermore connected by normally-off equalization transistors which are enabled by a first clock signal. The bit lines are further connected by normally-off resistive equalization transistors whose resistance is significant in conducting conditions. The equalization transistors are enabled by a first clock signal and the resistive equalization transistor are enabled by a second clock signal which has a duration that extends longer than the first clock signal. The memory cell reading circuit decreases the "read" time required for a memory cell, as compared to reading circuits previously used.

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