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公开(公告)号：JPH1027485A
公开(公告)日：1998-01-27
申请号：JP5951997
申请日：1997-03-13
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , BARCELLA ANTONIO , ROLANDI PAOLO , FONTANA MARCO
Abstract: PROBLEM TO BE SOLVED: To decrease the number of connecting lines connected between the one side of a pad and the other side of a pad of a memory device to reduce an area of a device. SOLUTION: A non-volatile memory device comprises an internal bus 3, a timer 8, and an enable/disable circuit 5 for enabling and disabling access to the internal bus. The timer 8 controls the internal bus, an enables transmitting an information signal of a memory device from a local auxiliary line on the internal bus 3 when the internal bus 3 is in an inactive period in a normal memory data reading cycle. The timer 8 controls an enable/disable means, and permits/negates access to the internal bus 3 by an information signal or data from/to a memory.
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公开(公告)号：JPH1027492A
公开(公告)日：1998-01-27
申请号：JP5919297
申请日：1997-03-13
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , BARCELLA ANTONIO , ROLANDI PAOLO , FONTANA MARCO
Abstract: PROBLEM TO BE SOLVED: To simplify the architecture of a data input/output management device by reducing the number of data transmission lines necessary for a memory and concentrating information thereof in a single point. SOLUTION: This device includes the following equipment and elements. That is, internal busses 1H and 1L for data transmission to a memory or from the memory are provided at least one bi-direction, and a redundant management line 2 transmits redundancy data associatively with the internal busses 1H and 1L. Switches 5L, 6L, 5H and 5L enable/unable the internal busses 1H and 1L to transmit data from the memory to the outside. A switch 9 enables/unables an external source to access the internal busses for data transmission to a memory matrix, and switches 8L. and 8H enable/unable the outside of the memory and a redundant line 2 to be connected during reading of the memory matrix or its programming.
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公开(公告)号：JPH1027488A
公开(公告)日：1998-01-27
申请号：JP7546997
申请日：1997-03-27
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , BARCELLA ANTONIO , ROLANDI PAOLO , FONTANA MARCO
Abstract: PROBLEM TO BE SOLVED: To enable adapting to a nonvolatile storage having less numbers of reference lines and particularly provided with a hierarchical decoder by providing the reference line and a data propagation/reproducing circuit, etc. SOLUTION: This circuit is divided to half matrices of two memories, and is provided with the reference lines 3, 3' and additional propagation/delay reproducing lines 4, 4' for reproducing propagation of signals along the reference lines 3, 3' with regard to respective matrices. These respective unit lines are provided with the same structure as respective general word lines of a storage. One side reference lines and propagation/delay reproducing lines of the half matrices 2-4, 2'-4' of two memories can be activated when the memory cells of the other half matrix are selected. Then, the reference lines synchronous and symmetrical related to the selection of the memory cells are provided for the read-out, and conditions for starting the precise and sure read-out of the memory cells selected by that are preset by the propagation/delay reproducing line 4.
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公开(公告)号：JP2540028B2
公开(公告)日：1996-10-02
申请号：JP32511294
申请日：1994-12-27
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , MACCARRONE MARCO
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公开(公告)号：JPH07326194A
公开(公告)日：1995-12-12
申请号：JP33746394
申请日：1994-12-28
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA
Abstract: PURPOSE: To obtain a voltage booster for a nonvolatile memory. CONSTITUTION: The voltage booster 1 comprises a charge pump 2 for generating a boost voltage Vboost on a boost line 3. The booster includes a voltage divider 5 to which a voltage V1 proportional to the boost voltage Vboost is applied, and also includes a comparator 6 to which a reference power 4 having a low reference voltage is applied, so that the charge pump 2 is put in its enable or disable state depending on a comparison result. A voltage limiter 8 is connected between the boost line 3 and ground. Further, a boost circuit 7 accelerates a voltage increase when the boost line is operated with low power, but a bus leading to the ground is made short to provide less power consumption.
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Patent Agency Ranking
公开(公告)号：JPH07249299A
公开(公告)日：1995-09-26
申请号：JP32511294
申请日：1994-12-27
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , MACCARRONE MARCO
Abstract: PURPOSE: To obtain an integrated programming circuit having redundancy by enabling the drive of a redundant programming load circuit according to the logical state of a data line through a switch circuit in response to a decoded output signal and inhibiting the drive of the other programming load circuit. CONSTITUTION: When a defective column address COLADD is supplied to a memory device, signals (OCO-OC3 and OCON-OC3N) are outputted from the identification code of a matrix part stored in a non-volatile register RR where this defective column address COLADD is stored. The output signals are supplied to a NAND gate 7 and in response to the output signal of the NAND gate 7, a switch circuit 6 enables the drive of a redundant programming load circuit PLOADR according to the logical state of a data line (DO-D15). At the same time, the gate 7 inhibits the drive of another programming load circuit (PLOADO-PLOAD15) through the switch circuit 6.
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公开(公告)号：DE69520659T2
公开(公告)日：2001-08-02
申请号：DE69520659
申请日：1995-01-26
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI
Abstract: A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurality of pairs of control lines are disclosed. Each cell has two branches connected in OR configuration to a common sensing line of the cell or of the multibit register. The logic states to be tested for coincidence are applied in a complemented form through a pair of lines to each cell, that is to the two branches of the cell. Each cell, permanently programmed in one or the other of its branches, intrinsically performs a comparison between its permanently programmed logic configuration and the configuration of the complemented control lines associated therewith. A great simplification is achieved in the overall circuitry of a redundance or reconfiguration system.
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公开(公告)号：DE69520659D1
公开(公告)日：2001-05-17
申请号：DE69520659
申请日：1995-01-26
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI
Abstract: A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurality of pairs of control lines are disclosed. Each cell has two branches connected in OR configuration to a common sensing line of the cell or of the multibit register. The logic states to be tested for coincidence are applied in a complemented form through a pair of lines to each cell, that is to the two branches of the cell. Each cell, permanently programmed in one or the other of its branches, intrinsically performs a comparison between its permanently programmed logic configuration and the configuration of the complemented control lines associated therewith. A great simplification is achieved in the overall circuitry of a redundance or reconfiguration system.
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公开(公告)号：DE69319886T2
公开(公告)日：1999-03-18
申请号：DE69319886
申请日：1993-03-31
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： OLIVO MARCO , PASCUCCI LUIGI
Abstract: There is described a semiconductor memory comprising a matrix of lines and columns of memory cells, wherein the columns (BL) are grouped together in sectors, each sector representing the portion of the matrix itself related to a data input/output line. Each sector is in turn divided into packets (1) of columns, and there are redundancy columns (BLR) suitable for replacing a matrix column (BL) containing defective memory cells. Each of the redundancy columns (BLR) is included in a respective packet (1). The memory also comprises control circuits (5,6,7) to execute the abovementioned replacement.
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公开(公告)号：DE69224576T2
公开(公告)日：1998-11-12
申请号：DE69224576
申请日：1992-08-27
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI
Abstract: A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection means driven through five buses for implementing a two-level decoding, thus driving a fractionary number of rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.
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