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    31.
    发明专利
    未知

    公开(公告)号：DE69012382D1

    公开(公告)日：1994-10-20

    申请号：DE69012382

    申请日：1990-03-12

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  RIVA CARLO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

    Abstract: A reference cell for reading EEPROM memory devices, capable of discharging any charges present in its own floating gate (3) without varying the geometry of the cell with respect to that of the associated memory cells and without requiring specific manufacturing steps. For this purpose, a switch element, for example a diode (D1), is provided between the floating gate (3) and the substrate (11) of the device and discharges any charges present in the floating gate toward the substrate during the cell idle state (in the absence of read signals)

    35.
    发明专利
    未知

    公开(公告)号：DE69305986T2

    公开(公告)日：1997-03-06

    申请号：DE69305986

    申请日：1993-07-29

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PIO FEDERICO ,  RIVA CARLO ,  LUCHERINI SILVIA C O SGS-THOMS

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells (2) including plural rows (3) and columns (4), with each row (3) being provided with a word line (WL) and a control gate line (CG) and each column (4) having a bit line (BL); the bit lines (BL), moreover, are gathered into groups or bytes (9) of simultaneously addressable adjacent lines. Each cell (2) in the matrix incorporates a floating gate transistor (12) which is coupled to a control gate (8), connected to the control gate line (CG), and is connected serially to a selection transistor (5); also, the cells (2) of each individual byte (9) share their respective source areas (6), which areas are structurally independent for each byte (9) and are led to a corresponding source addressing line (SL) extending along a matrix column (7).

    36.
    发明专利
    未知

    公开(公告)号：DE69025854D1

    公开(公告)日：1996-04-18

    申请号：DE69025854

    申请日：1990-10-24

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

    IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L21/82 ,  H01L27/02 ,  G11C16/04

    Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

    39.
    发明专利
    未知

    公开(公告)号：IT1230363B

    公开(公告)日：1991-10-18

    申请号：IT2140289

    申请日：1989-08-01

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： RIVA CARLO

    IPC: G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C

    Abstract: The EEPROM memory cell with 100% redundancy includes two tunnel storage elements (10, 18; 26, 30) which are connected in parallel between a common source voltage (16) and an enabling transistor (22) which is controlled by a transfer terminal (24) and leads to a bit line (14), with respective sensing transistors (12, 28) arranged in series with respect to the storage elements. According to the invention, the cell furthermore includes an auxiliary enabling transistor (40) which is arranged in series on the source and is controlled by the transfer terminal.

    40.
    发明专利
    未知

    公开(公告)号：IT1228822B

    公开(公告)日：1991-07-04

    申请号：IT1987589

    申请日：1989-03-23

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  RIVA CARLO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C

    Abstract: A reference cell for reading EEPROM memory devices, capable of discharging any charges present in its own floating gate (3) without varying the geometry of the cell with respect to that of the associated memory cells and without requiring specific manufacturing steps. For this purpose, a switch element, for example a diode (D1), is provided between the floating gate (3) and the substrate (11) of the device and discharges any charges present in the floating gate toward the substrate during the cell idle state (in the absence of read signals)

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