公开(公告)号：JPS61198625A

公开(公告)日：1986-09-03

申请号：JP19692285

申请日：1985-09-06

Applicant: SONY CORP

Inventor： NISHIYAMA KAZUO ,  YANADA TETSUNOSUKE ,  ARAI MICHIO

IPC: H01L21/26 ,  H01L21/265

Abstract: PURPOSE:To enable the electrical activation of an ion-implanted region at high temperature in a short time and the uniformity of the seat resistance in a semiconductor substrate, by a method wherein ion implantation is performed to the substrate surface, and the ion-implanted region is activated by heating on irradiation with infrared lamp rays from both main surfaces of the substrate. CONSTITUTION:After ion implantation to the surface of a semiconductor sub strate, the ion-implanted region is activated by heating on irradiation with infrared lamp rays having a continuous wavelength distribution in a range of 0.4-4.0mum from both surfaces of the substrate by using an infrared lamp. Annealing by this infrared lamp ray irradiation can contrive the electrical activation of the ion-implanted region in a short annealing time of 1/10-1/100 of the conventional time of electric furnace annealing, and can solve the conven tional problems resulting from long-time annealing. Besides, because of several seconds of irradiation with infrared lamp rays, irradiation only from one surface is liable to cause crystal defects due to stress by the generation of thermal distortion in the substrate. Since this invention includes irradiation from both main surfaces of the substrate, thermal distortion and crystal defects do not generate.

公开(公告)号：JPS6098682A

公开(公告)日：1985-06-01

申请号：JP20624583

申请日：1983-11-02

Applicant: SONY CORP

Inventor： DOUSEN MASASHI ,  ARAI MICHIO

IPC: H01L29/808 ,  H01L21/337 ,  H01L29/80

Abstract: PURPOSE:To reduce the side wall capacitance by a method wherein the second semiconductor layer having a larger energy gap than the first semiconductor layer of the first conductivity type is provided thereon, and a semiconductor layer of the second conductivity type is provided in the second semiconductor layer. CONSTITUTION:The first N type semiconductor layer 5 and the second N type semiconductor layer 6 are formed on a GaAs compound semiconductor substrate 4. The layer 6 is made up of a semiconductor layer having an energy gap larger than the layer 5. The gate region 7 is formed by introduction of a P type impurity to the layer 6. This manner reduces the capacitance per unit area in the side wall section ja.

公开(公告)号：JPS59105376A

公开(公告)日：1984-06-18

申请号：JP21586682

申请日：1982-12-09

Applicant: Sony Corp

Inventor： ARAI MICHIO ,  KATOU YOUJI

IPC: H01L29/808 ,  H01L21/265 ,  H01L21/337 ,  H01L29/80

CPC classification number: H01L29/80

Abstract: PURPOSE:To improve the high frequency characteristic and high speed operation by enhancing mutual conductance and reducing gate capacitance by deeply forming the second region, the third region, and a gate region in this order so that the second region becomes the deepest. CONSTITUTION:Si ions are implanted via a mask of photo resist 12 into one main surface of a semi-insulation GaAs substrate 11, thus forming an N type semiconductor region 13 serving as so-called a channel layer which includes a source and a drain. Next, after removing the mask 12, the substrate 11 is adhered in opposition to another GaAs substrate in H2 gas containing AsH3, and capless annealing treatment is performed. Then, an Si nitride film 14 is adhesion-formed on one main surface of the substrate 11, the part corresponding to the gate part of this Si nitride film 14 is selectively removed by the plasma etching with CF4+O2 gas via a mask of photo resist, resulting in the formation of a window hole 16. Further, a high resistant region (i.e. N type region of a low concentration) 17 is so formed as to be superposed on an N type semiconductor region 13, and a gate region 19 of the second semiconductivity type, i.e., P type is formed by selectively diffusion Zn through the same window hole 16 by the Si nitride film 14.

Abstract translation: 目的：为了使第二区域变得最深，为了通过深度地形成第二区域，第三区域和栅极区域，通过增强互导性和降低栅极电容来改善高频特性和高速度操作。 构成：通过光致抗蚀剂12的掩模将Si离子注入到半绝缘GaAs衬底11的一个主表面中，从而形成用作所谓的包括源极和漏极的沟道层的N型半导体区域13。 接下来，在除去掩模12之后，将衬底11与含有AsH 3的H 2气体中的另一个GaAs衬底相对地进行粘附，并进行无电极退火处理。 然后，在衬底11的一个主表面上附着形成氮化硅膜14，通过CF4 + O2气体的等离子体蚀刻通过照片掩模选择性地除去与该氮化硅膜14的栅极部相对应的部分 形成窗口16.此外，高阻抗区域（即，低浓度的N型区域）17被形成为叠置在N型半导体区域13上，并且栅极区域19形成为 通过由氮化硅膜14通过相同的窗孔16选择性地扩散Zn而形成第二半导体型，即P型。

公开(公告)号：JPS57124430A

公开(公告)日：1982-08-03

申请号：JP919581

申请日：1981-01-23

Applicant: Sony Corp

Inventor： NISHIYAMA KAZUO ,  ARAI MICHIO ,  NAKAJIMA HIDEHARU

IPC: H01L21/28

CPC classification number: H01L21/28

Abstract: PURPOSE:To shorten the processing time of sintering as well as to prevent the punch-through of the electrode material for the subject semiconductor device by a method wherein infrared rays are irradiated on the main surface of the semiconductor substrate whereon an electrode material was evaporated. CONSTITUTION:The electrode material such as aluminum and the like is evaporated on the main surface of the semiconductor substrate 1, and after patterning is performed, the substrate is arranged in a quartz pipe 2. Infrared ray lamp devices (tungsten lamp, for example) 4 are arranged at the upper and the lower parts on the outside of the quartz pipe 2, and an incoherent beam of light with a wavelength range of 0.4-4.0mum is irradiated from the lamp device 4. This irradiated beam of light is reflected by a parabolic reflecting mirror 5, and uniformly irradiated on the semiconductor substrate 1. A high-temperature and short-time heat treatment is performed by heating up the electrode material with the irradiated beam of light. Accordingly, the diffusing into the semiconductor of the electrode material can be suppressed, and an excellent ohmic contact having no punch-through can be obtained for a shallow junction too.

Abstract translation: 目的：为了缩短烧结的处理时间，并且通过其中红外线照射在电极材料蒸发的半导体衬底的主表面上的方法来防止对象半导体器件的电极材料的穿透。 构成：在半导体基板1的主表面上蒸发铝等电极材料，在图​​案化之后，将基板配置在石英管2中。红外线灯装置（例如钨灯） 4布置在石英管2的外侧的上部和下部，并且从灯装置4照射波长范围为0.4-4.0μm的非相干光束。该照射的光束被反射 抛物面反射镜5，并且均匀地照射在半导体基板1上。通过用照射的光束对电极材料进行加热来进行高温和短时间的热处理。 因此，可以抑制向电极材料的半导体的扩散，并且对于浅结也可以获得不穿孔的优异的欧姆接触。

公开(公告)号：JP2004029399A

公开(公告)日：2004-01-29

申请号：JP2002185867

申请日：2002-06-26

Applicant: Sony Corp ,  ソニー株式会社

Inventor： ARAI MICHIO

IPC: G09G3/34 ,  G09F9/00 ,  G09F9/30 ,  G09G3/20

Abstract: PROBLEM TO BE SOLVED: To realize handwritten display of a practical level in a display device or the like called as electronic paper.
SOLUTION: Handwritten input information is displayed on the display device in which pixels are selectively colored by power supply and the colored state is maintained even after interrupting the power supply. In this case, an image is directly drawn on a display panel on the basis of position information (handwritten input information) from a position information detection means to attain real time display. After high speed direct drawing, additional write may be permitted. It is also available to directly draw an image based on the position information from the position information detection means in a state of being superposed on an image display based on external picture information.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JPS62219424A

公开(公告)日：1987-09-26

申请号：JP6318086

申请日：1986-03-20

Applicant: SONY CORP

Inventor： ISHIBASHI AKIRA ,  ARAI MICHIO

IPC: H01L21/20 ,  H01J1/30 ,  H01J1/308 ,  H01L21/027 ,  H01L21/30

Abstract: PURPOSE:To improve quick-response performance, reduce power consumption, and enhance resolution by carrying out an electron emission in the vertical direction of a superlattice semiconductor layer. CONSTITUTION:First and second compound semiconductor thin film layers 2a, 2b are formed on a semiconductor substrate 1. And, an electrode 4 is arranged on the supperlattice semiconductor layer 2 composed of the thin film layers 2a, 2b. The electrode 4 is formed in a ring shape or the like so as to emit an electron through the center portion thereof. The surface of the semiconductor layer 2 forming said electron emitting portion is covered with a cap layer 7 comprising an epitaxy layer made of GaAs or the like for protecting said surface. Beside, the back face of the substrate 1 is covered with the other electrode 5 in ormic connection and a power source 6 is set between electrodes 4 and 5. therefore, it is possible to emit an electron (e) from the cap layer 7.

公开(公告)号：JPS61222217A

公开(公告)日：1986-10-02

申请号：JP6432885

申请日：1985-03-28

Applicant: SONY CORP

Inventor： AKIMOTO KATSUHIRO ,  DOUSEN MASASHI ,  ARAI MICHIO

IPC: H01L21/203

Abstract: PURPOSE:To execute growth at a low cell temperature without reducing the growing speed, by employing a plural of cells for a molecular beam of at least one of elements constituting compound semiconductor. CONSTITUTION:A plural of cells are employed for a molecular beam of at least one of elements constituting compound semiconductor. For example, an MBE apparatus which has several Ga cells 2 and several As cells 3 in a growth chamber evacuated into very high vacuum ( -10 Torr) and which has an introducing inlet 4 for H2 gas, is employed. Under a condition in which H2 gas with about (2-5)X10 Torr is being introduced preliminarily in the growth chamber 1, heating every cell 2, 3 results in Ga and As molecular beams, which are bumped to a substrate 5 being heated preliminarily to a given temperature, thus to epitaxial-grow GaAs.

公开(公告)号：JPS6159872A

公开(公告)日：1986-03-27

申请号：JP18213184

申请日：1984-08-31

Applicant: Sony Corp

Inventor： ARAI MICHIO ,  DOSEN MASASHI

IPC: H01L29/205 ,  H01L21/331 ,  H01L29/10 ,  H01L29/73 ,  H01L29/735

CPC classification number: H01L29/735 ,  H01L29/1008

Abstract: PURPOSE:To enhance the current amplification factor by forming a current path by semiconductor injection carrier in a lateral structure on a semi- insulating region out of the third region having a high impurity density. CONSTITUTION:A non-impurity-doped AlXGa-xAs 0

Abstract translation: 目的：通过在具有高杂质密度的第三区域的半绝缘区域上的横向结构中形成由半导体注入载体形成电流路径来增强电流放大系数。 构成：在半绝缘GaAs半导体衬底11的一个主表面上形成非杂质掺杂的Al x Ga x As 0

公开(公告)号：JPS60106177A

公开(公告)日：1985-06-11

申请号：JP21387283

申请日：1983-11-14

Applicant: SONY CORP

Inventor： ARAI MICHIO ,  WADA MASARU ,  TAIRA KENICHI

IPC: H01L29/808 ,  H01L21/337 ,  H01L21/66 ,  H01L29/80

Abstract: PURPOSE:To enable to surely realize a junction type FET having the prescribed pinch- off voltage Vp value by a method wherein the presumption of the pinch-off voltage Vp value can be accurately performed properly in the manufacturing process of the junction type FET. CONSTITUTION:A window 5 is protrudedly provided on a part of an Si3N4 layer 4 on a region 2, which is to finally become the gate region of the FET to be used as a circuit element on the region 2, and at the same time, a pair of windows 6a and 6b are protrudedly provided on a region 3. P type impurities, Zn, for example, are diffused on each region 2 and 3 through these window 5, 6a and 6b, and a P type gate region 5 and a pair of regions 8a and 8b for characteristic detection are respectively formed. The characteristics through this gate regionm 5 are presumptively detected indirectly. This detection is performed by a way that electromagnetic needles consisting of Cu, etc., respectively, that is, probes 9a and 9b, are set up in contact respectively on the regions 8a and 8b for characteristic detection and the impedance between both probes is measured. By this measurement, the pinch-off voltage of the FET to be used as a circuit element becomes known. On the basis of this result, additional diffusions are performed on the regions 7, 8a and 8b at need in a depth, by which the purposive pinch-off voltage Vp value of the FET can be obtained, and the depth is set at the prescribed depth.

公开(公告)号：JPS51892A

公开(公告)日：1976-01-07

申请号：JP7040974

申请日：1974-06-20

Applicant: SONY CORP

Inventor： ARAI MICHIO

IPC: H01L27/146 ,  H01L29/80 ,  H01L31/10 ,  H04N3/14 ,  H04N5/335 ,  H04N5/357