公开(公告)号：DE69313430D1

公开(公告)日：1997-10-02

申请号：DE69313430

申请日：1993-12-22

Applicant: SONY CORP

Inventor： UCHINO KATSUHIDE ,  MAEKAWA TOSHIKAZU ,  ICHIKAWA HIROAKI

IPC: G02F1/133 ,  G02F1/1345 ,  G02F1/136 ,  G02F1/1368 ,  G09G3/36 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

Abstract: A liquid crystal display device of the active matrix type which prevents residual of charge in liquid crystal picture elements with respect to time. The active matrix liquid crystal display device includes liquid crystal picture elements formed from a liquid crystal layer held between picture element electrodes arranged in a matrix and common electrodes opposing to the picture element electrodes, and picture element transistors corresponding to the liquid crystal picture elements. While a predetermined reference potential is supplied to the common electrode, image signals are applied to the individual picture element electrodes by way of signal lines and picture element transistors to effect ac driving of the liquid crystal picture elements. Discharge means for connecting the common electrodes and the picture element electrodes to an equivalent potential to each other is provided to discharge the charge remaining in the liquid crystal picture elements thereby to prevent the variation of the reference potential.

公开(公告)号：DE3366801D1

公开(公告)日：1986-11-13

申请号：DE3366801

申请日：1983-04-16

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  MAEKAWA TOSHIKAZU ,  OHTSU KOJI

IPC: H01L27/146 ,  H04N5/374 ,  H04N5/30 ,  H01L27/14 ,  H04N3/15

公开(公告)号：DE3332443A1

公开(公告)日：1984-03-29

申请号：DE3332443

申请日：1983-09-08

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  MAEKAWA TOSHIKAZU ,  OTSU KOUJI

IPC: G09G3/36 ,  G09G3/22 ,  G11C19/00 ,  G11C19/18 ,  G11C19/28 ,  H03K5/15 ,  H04N3/14

Abstract: A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the source follower transistor, the signal from the source follower transistor is supplied through a first transmission gate to a next stage, and also led out to an output terminal. Further, the circuit formed of the source follower transistor and the first transmission gate is sequentially connected and the source follower transistor and the first transmission gate are alternately driven with different phases to each other whereby the input signal is sequentially transmitted at each stage. Furthermore, a second transmission gate is connected between the output terminal of the source follower transistor and the ground in which after the output signal at the output terminal rises up and falls down once, the second transmission gate is turned on by the signal relating to the output from the stages following the succeeding stage to thereby make the level of the signal when the output signal at the output terminal falls down stable. Thus, undesired potential fluctuation is not generated on the output line.

公开(公告)号：MY118119A

公开(公告)日：2004-09-30

申请号：MYPI9501027

申请日：1995-04-20

Applicant: SONY CORP

Inventor： MAEKAWA TOSHIKAZU

IPC: G02F1/133 ,  G09G3/36 ,  G11C7/10 ,  G11C8/04 ,  G11C19/00 ,  H04N3/12 ,  H04N3/27 ,  H04N5/66

Abstract: AN ACTIVE MATRIX DISPLAY DEVICE COMPRISES A PLURALITY OF PIXELS, A VERTICAL SCANNING CIRCUIT (10), A HORIZONTAL ADDRESSING CIRCUIT (1), A WIDE INPUT SWITCH ELEMENT (W) AND A NORMAL INPUT SWITCH ELEMENT (N). THE PLURALITY OF PIXELS ARE ARRAYED IN A MATRIX SHAPE. THE VERTICAL SCANNING CIRCUIT (10) SEQUENTIALLY SELECTS PIXELS EVERY LINE. THE HORIZONTAL ADDRESSING CIRCUIT (1) DOT-SEQUENTIALLY ADDRESSES SELECTED LINE PIXELS AND HAS A SHIFT REGISTER CONSTITUTED BY A NUMBER OF MULTI-STAGE CONNECTED FLIP-FLOPS, THE NUMBER OF WHICH CORRESPONDS TO THE TOTAL NUMBER OF ROWS OF PIXELS. EACH FLIP-FLOP IS EQUIPPED WITH A PAIR OF INPUT/OUTPUT TERMINALS (3) AND A PRESCRIBED START PULSE IS TRANSFERRED EVERY STAGE. THE WIDE INPUT SWITCH ELEMENT (W) INPUTS A START PULSE TO AN INPUT TERMINAL OF A FLIP-FLOP POSITIONED AT A LEADING STAGE DURING WIDE DISPLAYING. THE NORMAL INPUT SWITCH ELEMENT (N) INPUTS A START PULSE TO AN INPUT OF A FLIP-FLOP POSITIONED AT A SPECIFIC INTERMEDIATE STAGE DURING NORMAL DISPLAYING. IT IS THEREFORE POSSIBLE TO SWITCH OVER BETWEEN A WIDE DISPLAY AND A NORMAL DISPLAY USING A HORIZONTAL ADDRESSING CIRCUIT (1) EMPLOYING A SINGLE SHIFT REGISTER (2). (FIGURE 1)

公开(公告)号：NO20021396D0

公开(公告)日：2002-03-20

申请号：NO20021396

申请日：2002-03-20

Applicant: SONY CORP

Inventor： KIDA YOSHITOSHI ,  NAKAJIMA YOSHIHARU ,  GOTO NAOSHI ,  MAEKAWA TOSHIKAZU ,  KATAOKA HIDEO

IPC: G02F1/13 ,  G02F1/1362 ,  G09G3/00 ,  G09G3/36 ,  G02F

Abstract: A liquid crystal display panel 1, to which an external horizontal drive circuit is connected in a TAB, COG, or other form, capable of performing aging by a substrate alone when image display is possible by connecting the external drive circuit, comprising an active matrix display area 2, a vertical drive circuit 4, and a horizontal aging circuit 5 for supplying signals to a plurality of source lines at one time provided on a substrate 3. Also, a medium- to small-sized active matrix type liquid crystal display apparatus used for a PDA etc. able to be produced at a high quality and a low cost without using a time sharing driving method and provided with a horizontal drive circuit as an external circuit, wherein a vertical drive circuit is formed integrally with a liquid crystal display area on a glass substrate by using low temperature PolySi TFTs, a horizontal drive circuit is connected to a liquid crystal display panel substrate by COG, and output terminals of a driver IC constituting the horizontal drive circuit and source lines Ls are in a one-to-one correspondence.

公开(公告)号：DE69423675T2

公开(公告)日：2000-08-31

申请号：DE69423675

申请日：1994-06-22

Applicant: SONY CORP

Inventor： MAEKAWA TOSHIKAZU

IPC: G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28

Abstract: A bidirectional signal transfer shift register with a simple circuit construction is disclosed together with suitable applications of the same. The bidirectional signal transfer shift register comprises a plurality of flipflops each having an input terminal and an output terminal in pair. The input and output terminals of the flipflops are connected successively in such a manner as to construct a multi-stage structure. A forward route gate element is interposed in a connection route between the output terminal of the front stage side one of each two adjacent front and rear ones of the flipflops and the input terminal of the rear stage side flipflop, and a reverse route gate element is interposed in another connection route between the output terminal of the rear stage side flipflop and the input terminal of the front stage side flipflop. Forward direction signal transmission processing and reverse direction signal transmission processing can be switchably selected by alternatively controlling the forward and reverse route gate elements to open or close.

公开(公告)号：DE69517851D1

公开(公告)日：2000-08-17

申请号：DE69517851

申请日：1995-04-21

Applicant: SONY CORP

Inventor： MAEKAWA TOSHIKAZU ,  UCHINO KATSUHIDE

IPC: G09G3/20 ,  G02F1/133 ,  G09G3/36

Abstract: To restrict an oscillation in the potential of a video line, caused by a high speed sampling rate, the active matrix display device is comprised of gate lines X forming rows, signal lines Y forming columns and liquid crystal pixels LC of the matrix arranged at crossing points of both lines. A V driver 1 scans in sequence each of the gate lines X and selects the liquid crystal pixels LC of one line for a corresponding horizontal period. The H driver 4 performs a sampling of the video signal VSIG for each of the signal lines Y and performs a writing of the video signal VSIG in the liquid crystal pixels LC the row selected during the corresponding horizontal period. Precharging means 5 supplies a predetermined precharging signal VPS to each of the signal lines Y just before writing the video signal VSIG for the liquid crystal pixels LC in one row. With such an arrangement as above, it is possible to reduce the charging or discharging amount in each of the signal lines Y when the video signal VSIG is sampled and further to restrict the oscillation of the potential in the video line 2.

公开(公告)号：DE69512301D1

公开(公告)日：1999-10-28

申请号：DE69512301

申请日：1995-04-21

Applicant: SONY CORP

Inventor： MAEKAWA TOSHIKAZU

IPC: G02F1/133 ,  G09G3/36 ,  G11C7/10 ,  G11C8/04 ,  G11C19/00 ,  H04N3/12 ,  H04N3/27 ,  H04N5/66

Abstract: An active matrix display device comprises a plurality of pixels, a vertical scanning circuit, a horizontal addressing circuit, a wide input switch element and a normal input switch element. The plurality of pixels are arrayed in a matrix shape. The vertical scanning circuit sequentially selects pixels every line. The horizontal addressing circuit dot-sequentially addresses selected line pixels and has a shift register constituted by a number of multi-stage connected flip-flops, the number of which corresponds to the total number of rows of pixels. Each flip-flop is equipped with a pair of input/output terminals and a prescribed start pulse is transferred every stage. The wide input switch element inputs a start pulse to an input terminal of a flip-flop positioned at a leading stage during wide displaying. The normal input switch element inputs a start pulse to an input of a flip-flop positioned at a specific intermediate stage during normal displaying. It is therefore possible to switch over between a wide display and a normal display using a horizontal addressing circuit employing a single shift register.

公开(公告)号：NL1011715A1

公开(公告)日：1999-10-08

申请号：NL1011715

申请日：1999-04-01

Applicant: SONY CORP

Inventor： MAEKAWA TOSHIKAZU ,  NODA KAZUHIRO

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  H04N5/66

Abstract: To readily realize a reduction in pel pitch and an increase in the number of pels, a V shift register is configured such that one pulse transfer stage is provided so as to correspond to two horizontal pel lines constituting a pel section of a liquid crystal panel. Further, a decoder decodes a signal output from each pulse transfer stage of the V shift register, thereby preparing a gate pulse for individually driving the pel line. The number of pulse transfer stages is made half that of a conventional pel drive circuit.

公开(公告)号：DE69313430T2

公开(公告)日：1998-05-20

申请号：DE69313430

申请日：1993-12-22

Applicant: SONY CORP

Inventor： UCHINO KATSUHIDE ,  MAEKAWA TOSHIKAZU ,  ICHIKAWA HIROAKI

IPC: G02F1/133 ,  G02F1/1345 ,  G02F1/136 ,  G02F1/1368 ,  G09G3/36 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

Abstract: A liquid crystal display device of the active matrix type which prevents residual of charge in liquid crystal picture elements with respect to time. The active matrix liquid crystal display device includes liquid crystal picture elements formed from a liquid crystal layer held between picture element electrodes arranged in a matrix and common electrodes opposing to the picture element electrodes, and picture element transistors corresponding to the liquid crystal picture elements. While a predetermined reference potential is supplied to the common electrode, image signals are applied to the individual picture element electrodes by way of signal lines and picture element transistors to effect ac driving of the liquid crystal picture elements. Discharge means for connecting the common electrodes and the picture element electrodes to an equivalent potential to each other is provided to discharge the charge remaining in the liquid crystal picture elements thereby to prevent the variation of the reference potential.