公开(公告)号：JPS62277732A

公开(公告)日：1987-12-02

申请号：JP12068986

申请日：1986-05-26

Applicant: SONY CORP

Inventor： MORITA YASUSHI ,  NODA SANEYA ,  HAYASHI HISAO ,  HOSHI TAEKO

IPC: H01L21/302 ,  H01L21/20 ,  H01L21/3065

Abstract: PURPOSE:To form a groove section having an excellent shape by selectively shaping a substance layer having different etching characteristics onto a single crystal semiconductor base body, selectively growing a single crystal semiconductor layer to an exposed section in an epitaxial manner and optionally removing the substance layer through etching. CONSTITUTION:A substance layer having etching characteristics different from silicon such as an SiO2 layer 5 is shaped onto one main surface of a single crystal semiconductor base body such as a single crystal silicon base body 1 in uniform thickness corresponding to the depth of a groove to be formed through a CVD method. The SiO2 layer 5 is patterned through anisotropic etching such as reactive ion etching, and the SiO2 layer 5 having equal width in the thickness direction is left only in a section to which the groove section is shaped. An silicon layer 6 is grown selectively only on the silicon base body 1 with no SiO2 layer 5 in an epitaxial manner by using the mixed gas of SiH4+ HCl or the mixed gas of SiH2Cl2+HCl. The SiO2 layer 5 is removed through etching by a solution such as an HF solution, thus forming the groove section 7 to the surface of the single crystal silicon base body.

公开(公告)号：JPS62272522A

公开(公告)日：1987-11-26

申请号：JP11583286

申请日：1986-05-20

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  MORITA YASUSHI ,  NODA SANEYA ,  HOSHI TAEKO

IPC: H01L21/205

Abstract: PURPOSE:To enhance the smoothness of a polycrystalline silicon semiconductor layer formed on an insulating layer by vapor growing a silicon semiconductor layer under specific pressure condition on the surface including the insulating layer of a silicon substrate on which the insulating layer is selectively formed on the surface. CONSTITUTION:A silicon semiconductor layer is vapor grown under the conditions of 550-600 deg.C at normal pressure or 900-1000 deg.C at 200Torr or lower on the surface including an insulating layer of a silicon substrate on which the insulating layer is selectively formed on the surface. When the growing temperature is 600 deg.C at normal pressure, the semiconductor layer formed on the single crystal silicon substrate has good reflectivity of wavelength of 280nm and also of 200nm, thereby providing high smoothness. When it is vapor grown at normal pressure when vapor growing at 900 deg.C, the surface smoothness of the semiconductor layer on the insulating layer is deteriorated so that the semiconductor layer at the normal pressure is not preferable. However, when reduced to 200Torr or 100Torr, the surface smoothness and crystallinity of the semiconductor layer on the insulating layer are excellent. Especially,when the pressure reducing degree is increased more, its reflecting spectrum is varied better.

公开(公告)号：JPS6224631A

公开(公告)日：1987-02-02

申请号：JP16295985

申请日：1985-07-25

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  MORITA YASUSHI

IPC: H01L21/322

Abstract: PURPOSE:To allow easy and effective gettering by applying a solution containing phosphorus to the opposite surface of the semiconductor element formation side of a semiconductor substrate and by heat-treating it. CONSTITUTION:An N layer 11, an N layer 12, and a P layer 13 are formed on a silicon substrate 1 to provide a planar P-N junction, and a SiO2 layer 24 is formed on an element formation surface. Then, when a solution 2 containing phosphorus is applied to the opposite surface of the element formation surface which is then heat-treated, the phosphorus in the solution 2 containing phosphorus enters the Si constituting the substrate 1, forming an N layer 3. This layer 3 absorbs a heavy metal, performing gettering.

公开(公告)号：JPH1056062A

公开(公告)日：1998-02-24

申请号：JP22781096

申请日：1996-08-09

Applicant: SONY CORP

Inventor： MORITA YASUSHI

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enable an insulating film which serves as an etching stopper for another insulating film to be etched high in stability and controllability. SOLUTION: An SiN film 26 and an SiO2 film 22 are etched using a photoresist film 23 as a mask, the resist film 23 is removed, and the SiN films 21 and 26 are etched at the same time. A high-molecular compound layer 24 formed on the surface and the like of the SiN film 21 is removed at the same time with the photoresist 23, so that the SiN film 21 and the polymer compound layer 24 are not required to be etched at the same time. Moreover, the SiO2 film 22 can be prevented from being etched together with the SiN film 21 by the SiN film 26.

公开(公告)号：JPH04342129A

公开(公告)日：1992-11-27

申请号：JP14258491

申请日：1991-05-17

Applicant: SONY CORP

Inventor： MUROYAMA MASAKAZU ,  MORITA YASUSHI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

Abstract: PURPOSE:To flatten the surface of an interlayer insulating film for a semiconductor device at a low temperature. CONSTITUTION:A substance which is used to form a flattening film 15 is set to a liquid-phase state; a film 14 whose surface is nearly flat (e.g. a water film) is formed, of the substance in the liquid-phase state, on the surface 13a of an interlayer insulating film 13. In succession, the formed film 14 is solidified; the flattening film 15 is formed. Then, the flattening film 15 and the interlayer insulating film 13 are etched back partly; the surface 13b of the interlayer insulating film 13 is flattened.

公开(公告)号：JPH03139858A

公开(公告)日：1991-06-14

申请号：JP27792989

申请日：1989-10-25

Applicant: SONY CORP

Inventor： SATO JUNICHI ,  GOCHO TETSUO ,  MORITA YASUSHI

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/762

Abstract: PURPOSE:To remove an insulating film at the outside of a trench and to make it possible to perform flat embedding even if a slope part is formed at the lower part of the side surface of the insulating film at the outside of the trench by forming an etching stop layer on a surface of a substrate before the formation of a trench beforehand. CONSTITUTION:An etching stop layer 6 is formed beforehand. A trench 2 and an insulating film 3 are formed. An insulating film 3a at the outside of the trench is returned to a horizontal state and etched. Thereafter, anisotropic etching is performed. Therefore the slope part at the bottom of the insulating film 3a at the outside of the trench can be completely removed. Thus, a space required for forming a resist film masking an insulating film 3 in the trench can be secured. The insulating film 3a at the outside of the trench can be completely removed. The surface part of the insulating film 3 in the trench is etched by anisotropic etching after the etching for restoring the horizontal state. Since the insulating film 3 is thickly formed by the thickness of the etching stop layer 6 originally, the surface of the insulating film 3 can be made flush with the height of the surface of the substrate by the anisotropic etching.

公开(公告)号：JPH0336271A

公开(公告)日：1991-02-15

申请号：JP16796789

申请日：1989-06-29

Applicant: SONY CORP

Inventor： MORITA YASUSHI

IPC: C23C16/48 ,  C23C16/50 ,  C23C16/511 ,  H01L21/31

Abstract: PURPOSE:To compensate the nonuniformity of a film and to obtain uniform film thickness by combinedly using a stage of forming a thin film by an ECR plasma CVD method and a stage of forming a thin film by a photo-CVD method. CONSTITUTION:An ECR plasma CVD method is used and a plasma stream 2 is introduced via a window 14 into a treatment chamber 15 to form a thin film on a base material 1, by which the thin film whose thickness is increased in the central part and reduced at the periphery is formed. Further, a photo-CVD method is used and light 4 is introduced through a photoirradiation window 5 to form a thin film on the base material 1, by which the thin film whose thickness is reduced in the central part and increased at the periphery is formed. By combinedly using both stages mentioned above, a thin film of uniform film thickness can be obtained.

公开(公告)号：JPH01189914A

公开(公告)日：1989-07-31

申请号：JP1529488

申请日：1988-01-25

Applicant: SONY CORP

Inventor： MORITA YASUSHI ,  NODA SANEYA

IPC: H01L21/76 ,  H01L21/205

Abstract: PURPOSE:To prevent semiconductor layers from being deteriorated in crystallinity near the interfaces with masking films in a process of selective epitaxy, by forming at least sidewalls of the masking films of a nitride, removing them and oxidizing sidewalls of the semiconductor layers. CONSTITUTION:Masking films 4 formed of a nitride at least in the sidewalls thereof are formed selectively on the surface of a semiconductor substrate 1 and then semiconductor layers 5, 7 are formed on the exposed regions 3, 6 of the semiconductor substrate 1 by means of the selective epitaxy. The nitride films 4 are then removed and the sidewalls of the semiconductor layers are oxidized. Namely, interfaces of the semiconductor layers 5, 7 are provided by oxidizing the sidewalls of the epitaxially deposited layers. In this manner, crystallinity of the semiconductor layers deposited by the selective epitaxy can be improved near the interfaces with the masking films.

公开(公告)号：JPS63299321A

公开(公告)日：1988-12-06

申请号：JP13552287

申请日：1987-05-29

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI ,  MORITA YASUSHI

IPC: H01L21/20 ,  H01L21/263 ,  H01L21/84

Abstract: PURPOSE:To form excellent boundary surfaces of each layer without development and mingling of foreign matter between layers, by forming three layers continuously, i.e., only by changing material gas in the same reaction chamber. CONSTITUTION:On an insulator 11, a first layer 1 containing nitrogen or carbon less than or equal to 20 atomic %, i.e., being composed of an amorphous silicon layer of Si1-xNx or Si1-xCx (0

公开(公告)号：JPS63100748A

公开(公告)日：1988-05-02

申请号：JP24553686

申请日：1986-10-17

Applicant: SONY CORP

Inventor： NODA JITSUYA ,  MORITA YASUSHI

IPC: H01L21/3205

Abstract: PURPOSE:To enhance safety by a method wherein, in an opening part wherein a semiconductor layer is formed and an electrical connection is obtained, a silicate glass layer containing an impurity is laminated on an insulating layer forming the opening part and the impurity is introduced in the semiconductor layer from this silicate glass layer at the time of formation of the semiconductor layer. CONSTITUTION:An SiO2 layer 2 and an impurity-containing PSG glass layer 3 are laminated and adhered on an Si substrate 1 with an element region being formed thereon, a reactive ion etching is performed and an opening part 4 is bored correspondingly to the element region. Then, a semiconductor layer 5, which comes into contact to the element region, is buried in the opening part 4, yet at this time, the semiconductor layer 5 is constituted of poly Si made to contain an impurity using SiH2Cl2-HCl-PH3-H2 gas, for example. As a heat treatment is sure to be associated with to this, the P being contained in the glass layer 3 is also injected simultaneously in the layer 5 and to make lower the impurity concentration in the gas used before is made possible. Accordingly, the riskiness due to work is reduced.