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公开(公告)号：AU545651B2
公开(公告)日：1985-07-25
申请号：AU6932081
申请日：1981-04-08
Applicant: SONY CORP
Inventor： SONEDA MITSUO
Abstract: A filter circuit comprising a charge transfer device of the type which includes first and second sets of charge storage devices, such as capacitors, the first and second sets of charge storage devices being supplied with first and second clock signals, respectively, and further including first and second sets of switches which are actuated in response to the first and second clock signals, respectively, each switch being operable, when actuated, to transfer charge between a charge storage device in one set and a charge storage device in the other set, thereby transferring a charge through succeeding switches to be temporarily stored in succeeding charge storage devices. A semiconductor element, such as a transistor, is actuated in response either to the first or to the second clock signals for transferring the charge stored in a first predetermined charge storage device to a second predetermined charge storage device. An output circuit is coupled to a preselected charge storage device for deriving an output signal from the filter circuit.
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公开(公告)号：DE3332443A1
公开(公告)日：1984-03-29
申请号：DE3332443
申请日：1983-09-08
Applicant: SONY CORP
Inventor： SONEDA MITSUO , MAEKAWA TOSHIKAZU , OTSU KOUJI
Abstract: A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the source follower transistor, the signal from the source follower transistor is supplied through a first transmission gate to a next stage, and also led out to an output terminal. Further, the circuit formed of the source follower transistor and the first transmission gate is sequentially connected and the source follower transistor and the first transmission gate are alternately driven with different phases to each other whereby the input signal is sequentially transmitted at each stage. Furthermore, a second transmission gate is connected between the output terminal of the source follower transistor and the ground in which after the output signal at the output terminal rises up and falls down once, the second transmission gate is turned on by the signal relating to the output from the stages following the succeeding stage to thereby make the level of the signal when the output signal at the output terminal falls down stable. Thus, undesired potential fluctuation is not generated on the output line.
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公开(公告)号：DE3045466A1
公开(公告)日：1981-08-27
申请号：DE3045466
申请日：1980-12-02
Applicant: SONY CORP
Inventor： TSUCHIYA TAKAO , SONEDA MITSUO , NAKAMURA ISA
IPC: G11C27/04 , G11C19/18 , H01L21/339 , H01L29/762 , H03H15/02
Abstract: A bucket brigaded device is provided which includes first and second clocking signal generators for generating a first set and a second set of clocking signals respectively, a plurality of successive capacitors for sequentially holding charge level representing an input signal, and a plurality of transistors for controlling the transfer of charge levels from one capacitor to another. Each of the transistors is connected between adjacent capacitors. The bucket brigaded device further comprises a first clocking signal driver for supplying one of the first set of clocking signals to each capacitor, and a second clocking signal driver for supplying one of the second set of clocking signals to each transistor.
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公开(公告)号：DE2951166A1
公开(公告)日：1980-07-03
申请号：DE2951166
申请日：1979-12-19
Applicant: SONY CORP
Inventor： TSUCHIYA TAKAO , SONEDA MITSUO
Abstract: A clocking signal drive circuit supplies at least one clocking signal in a charge transfer device which has a plurality of successive capacitive storage elements for sequentially holding a charge level representing a time sampled input signal, with each of the capacitive storage elements having a clocking electrode for receiving one of a plurality of clocking signals so that the charge level representing the time sampled input signal is transferred from one to another of the capacitive storage means in succession in response to the clocking signals. The clocking signal drive circuit includes a clocking signal generator having an output at which the generator provides a clocking control signal, and a pair of complementary transistors each having first, second, and control electrodes, with the control electrode of the complementary transistors being connected together and to the output of the clocking signal generator and the first electrodes of the complementary transistors being connected together and to the clocking electrode of at least one of the capacitive storage elements. In one embodiment of the invention the clocking signal drive circuit functions as an output device for detecting the charge level on at least one of the capacitive storage elements of the charge transfer device, and further includes a detector for determining the amount of current which flows from the clocking signal drive circuit to the clocking electrode or electrodes to which it is connected.
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公开(公告)号：AU5403679A
公开(公告)日：1980-06-26
申请号：AU5403679
申请日：1979-12-19
Applicant: SONY CORP
Inventor： TSUCHIYA TAKAO , SONEDA MITSUO
Abstract: A clocking signal drive circuit supplies at least one clocking signal in a charge transfer device which has a plurality of successive capacitive storage elements for sequentially holding a charge level representing a time sampled input signal, with each of the capacitive storage elements having a clocking electrode for receiving one of a plurality of clocking signals so that the charge level representing the time sampled input signal is transferred from one to another of the capacitive storage means in succession in response to the clocking signals. The clocking signal drive circuit includes a clocking signal generator having an output at which the generator provides a clocking control signal, and a pair of complementary transistors each having first, second, and control electrodes, with the control electrode of the complementary transistors being connected together and to the output of the clocking signal generator and the first electrodes of the complementary transistors being connected together and to the clocking electrode of at least one of the capacitive storage elements. In one embodiment of the invention the clocking signal drive circuit functions as an output device for detecting the charge level on at least one of the capacitive storage elements of the charge transfer device, and further includes a detector for determining the amount of current which flows from the clocking signal drive circuit to the clocking electrode or electrodes to which it is connected.
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Patent Agency Ranking
公开(公告)号：GB2190808B
公开(公告)日：1989-12-13
申请号：GB8708490
申请日：1987-04-09
Applicant: SONY CORP
Inventor： SONEDA MITSUO
IPC: G11C11/419 , G11C7/06 , H03K3/011 , H03K3/356
Abstract: An apparatus for sensing an electric charge appearing on at least one bit line of a memory cell comprises a pair of P-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, a pair of N-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, both pairs of the PMOS and NMOS transistors carrying out latch operations according to control signals supplied to their sources to sense the electric charge appearing on either a first or second bit line. In at least one of the pairs of PMOS and NMOS transistors, the gate of each MOS transistor is connected to either the first or second bit line via a capacitor, a first switching element is disposed between the drain of each MOS transistor and gate thereof, and a second switching element is disposed between the drain of each MOS transistor and a junction to either the first or second bit line. When control voltages applied to both sources of the PMOS transistors and NMOS transistors are changed and the switching elements are switched over during a precharge interval and sensing operation interval, the capacitors store voltages according to the respective threshold voltages of the PMOS and NMOS transistors so that divergence in the threshold voltages can be compensated for.
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公开(公告)号：CA1230651A
公开(公告)日：1987-12-22
申请号：CA435542
申请日：1983-08-29
Applicant: SONY CORP
Inventor： SONEDA MITSUO , MAEKAWA TOSHIKAZU , OTSU KOUJI
Abstract: A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the source follower transistor, the signal from the source follower transistor is supplied through a first transmission gate to a next stage, and also led out to an output terminal. Further, the circuit formed of the source follower transistor and the first transmission gate is sequentially connected and the source follower transistor and the first transmission gate are alternately driven with different phases to each other whereby the input signal is sequentially transmitted at each stage. Furthermore, a second transmission gate is connected between the output terminal of the source follower transistor and the ground in which after the output signal at the output terminal rises up and falls down once, the second transmission gate is turned on by the signal relating to the output from the stages following the succeeding stage to thereby make the level of the signal when the output signal at the output terminal falls down stable. Thus, undesired potential fluctuation is not generated on the output line.
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公开(公告)号：DE3716803A1
公开(公告)日：1987-12-10
申请号：DE3716803
申请日：1987-05-19
Applicant: SONY CORP
Inventor： SONEDA MITSUO
IPC: G11C11/419 , G11C7/06 , H03K3/011 , H03K3/356
Abstract: An apparatus for sensing an electric charge appearing on at least one bit line of a memory cell comprises a pair of P-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, a pair of N-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, both pairs of the PMOS and NMOS transistors carrying out latch operations according to control signals supplied to their sources to sense the electric charge appearing on either a first or second bit line. In at least one of the pairs of PMOS and NMOS transistors, the gate of each MOS transistor is connected to either the first or second bit line via a capacitor, a first switching element is disposed between the drain of each MOS transistor and gate thereof, and a second switching element is disposed between the drain of each MOS transistor and a junction to either the first or second bit line. When control voltages applied to both sources of the PMOS transistors and NMOS transistors are changed and the switching elements are switched over during a precharge interval and sensing operation interval, the capacitors store voltages according to the respective threshold voltages of the PMOS and NMOS transistors so that divergence in the threshold voltages can be compensated for.
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公开(公告)号：GB2108351B
公开(公告)日：1985-01-30
申请号：GB8214621
申请日：1982-05-19
Applicant: SONY CORP
Inventor： SONEDA MITSUO , NOGUCHI TAKASHI , OHTSU TAKAJI
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公开(公告)号：AU532271B2
公开(公告)日：1983-09-22
申请号：AU5403679
申请日：1979-12-19
Applicant: SONY CORP
Inventor： TSUCHIYA TAKAO , SONEDA MITSUO
Abstract: A clocking signal drive circuit supplies at least one clocking signal in a charge transfer device which has a plurality of successive capacitive storage elements for sequentially holding a charge level representing a time sampled input signal, with each of the capacitive storage elements having a clocking electrode for receiving one of a plurality of clocking signals so that the charge level representing the time sampled input signal is transferred from one to another of the capacitive storage means in succession in response to the clocking signals. The clocking signal drive circuit includes a clocking signal generator having an output at which the generator provides a clocking control signal, and a pair of complementary transistors each having first, second, and control electrodes, with the control electrode of the complementary transistors being connected together and to the output of the clocking signal generator and the first electrodes of the complementary transistors being connected together and to the clocking electrode of at least one of the capacitive storage elements. In one embodiment of the invention the clocking signal drive circuit functions as an output device for detecting the charge level on at least one of the capacitive storage elements of the charge transfer device, and further includes a detector for determining the amount of current which flows from the clocking signal drive circuit to the clocking electrode or electrodes to which it is connected.
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