公开(公告)号：FR2868203A1

公开(公告)日：2005-09-30

申请号：FR0450610

申请日：2004-03-29

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  CHEVALIER PASCAL

IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/10 ,  H01L29/737

Abstract: L'invention concerne un procédé de formation d'un transistor bipolaire dans un substrat semiconducteur (20) d'un premier type de conductivité, comportant les étapes suivantes :a) former sur le substrat une couche monocristalline de silicium-germanium (22) ;b) former une couche de silicium monocristallin (24) fortement dopée d'un second type de conductivité ;c) former une couche d'oxyde de silicium (26) ;d) ouvrir une fenêtre (28) dans les couches d'oxyde de silicium et de silicium ;e) former sur les parois de la fenêtre un espaceur (30) en nitrure de silicium ;f) éliminer la couche de silicium-germanium depuis le fond de la fenêtre ;g) former dans la cavité (31) résultante de l'élimination précédente une couche semiconductrice monocristalline (32) fortement dopée du second type de conductivité ; eth) former dans ladite fenêtre l'émetteur (36) du transistor.

公开(公告)号：FR2858877A1

公开(公告)日：2005-02-18

申请号：FR0350418

申请日：2003-08-11

Applicant: ST MICROELECTRONICS SA

Inventor： MARTINET BERTRAND ,  MARTY MICHEL ,  CHEVALIER PASCAL ,  CHANTRE ALAIN

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737

Abstract: A method for forming a heterojunction bipolar transistor including the steps of: forming in a semiconductor substrate a collector area of a first doping type; growing by epitaxy above a portion of the collector area a silicon/germanium layer of a second doping type forming a base area; forming above the silicon/germanium layer a sacrificial emitter formed of a material selectively etchable with respect to the silicon/germanium layer and with respect to the layers and consecutively-formed insulating spacers; forming first insulating spacers on the sides of the sacrificial emitter; growing by epitaxy a silicon layer above the exposed portions of the silicon/germanium layer; forming second insulating spacers adjacent to the first spacers and laid on the silicon layer; covering the entire structure with an insulating layer; partially removing the insulating layer above the sacrificial emitter and removing the sacrificial emitter; filling the space previously taken up by the sacrificial emitter with a semiconductor material of the first doping type.

公开(公告)号：FR2806831B1

公开(公告)日：2003-09-19

申请号：FR0003845

申请日：2000-03-27

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  DUTARTRE DIDIER ,  BAUDRY HELENE

IPC: H01L21/331 ,  H01L29/737

Abstract: A method for the fabrication of a bipolar transistor consists of forming, using non-selective epitaxy, a semiconductor region with a silicon-germanium heterojunction (1) extending over an active region (ZA) of a semiconductor substrate and an insulating region (STI) delimiting the active region, and incorporating the region of the intrinsic base of the transistor; an emitter region (8) situated above the active region and coming into contact with the upper surface of the heterojunction semiconductor region (1); a layer of polysilicon (30) forming the region of the extrinsic base of the transistor, situated either side of the emitter region (8) and separated from the heterojunction semiconductor region by a separation layer incorporating an electrical liaison conductor (74) part situated in the external neighbourhood of the emitter region, this liaison part assuring an electrical contact between the extrinsic base and the intrinsic base. An Independent claim is included for such a bipolar transistor.

公开(公告)号：FR2813707A1

公开(公告)日：2002-03-08

申请号：FR0011419

申请日：2000-09-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  CHANTRE ALAIN ,  MARTY MICHEL ,  JOUAN SEBASTIEN

IPC: H01L21/331 ,  H01L29/10 ,  H01L21/28

Abstract: Fabrication of a bipolar transistor on a monocrystalline silicon substrate (1) with a first type of conductivity incorporates a stage of carbon implantation at the surface of the substrate followed by annealing, before epitaxial formation of the base of the transistor in the form of a multi-layer (T) semiconductor incorporating at least one lower layer (4), a median heavily doped layer (5) with a second type of conductivity and a upper layer (6) which contacts a heavily doped emitter (9) with the first type of conductivity. An Independent claim is included for a hetero-junction bipolar transistor produced.

公开(公告)号：FR2803091B1

公开(公告)日：2002-03-08

申请号：FR9916283

申请日：1999-12-22

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  FELLOUS CYRIL

IPC: H01L21/223 ,  H01L21/331 ,  H01L21/8222

公开(公告)号：FR2799048A1

公开(公告)日：2001-03-30

申请号：FR9911895

申请日：1999-09-23

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

IPC: H01L29/73 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/737 ,  H01L21/00 ,  H01L21/22 ,  H01L29/732

Abstract: Bipolar transistor fabrication includes a step of producing a base region (8) comprising an extrinsic base (800) and an intrinsic base, and a step of producing an emitter block having a narrower lower part located in an emitter-window above the intrinsic base. Production of the extrinsic base (800) involves dopant implantation after defining the emitter-window, on both sides at a determined distance from the lateral limits of the emitter-window, with self-alignment about the emitter-window, and before emitter block formation. An oxide block (13) is formed on an insulating layer located above the intrinsic base. The oxide block (13) has a narrower lower part (130) located in an etched hole of the insulating layer and whose dimensions correspond to those of the emitter-window, and an upper wider part (131) resting on the insulating layer. The lateral sides of the etched hole of the insulating layer are self-aligned with the lateral sides (FV) of the upper part of the oxide block. Ion implantation of the extrinsic base is formed on both sides of the upper part of the oxide block (13).

公开(公告)号：FR3043852B1

公开(公告)日：2017-12-22

申请号：FR1560911

申请日：2015-11-13

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： FERROTTI THOMAS ,  BEN BAKIR BADHISE ,  CHANTRE ALAIN ,  CREMER SEBASTIEN ,  DUPREZ HELENE

IPC: H01S5/187

公开(公告)号：FR2891087A1

公开(公告)日：2007-03-23

申请号：FR0552818

申请日：2005-09-20

Applicant: ST MICROELECTRONICS SA

Inventor： CHEVALIER PASCAL ,  CHANTRE ALAIN

IPC: H01L29/732 ,  H01L21/331

Abstract: L'invention concerne un transistor bipolaire comprenant une région de base (30) reposant par sa face inférieure sur une région de collecteur (1) et entourée d'une première couche isolante (2), une région conductrice de contact de base (3) en contact avec une région périphérique supérieure externe de la région de base, une deuxième région isolante (8) en contact avec une région périphérique supérieure intermédiaire de la région de base, une région d'émetteur (32) en contact avec la partie centrale de la région de base. Le niveau de la partie centrale est plus élevé que le niveau de ladite partie intermédiaire.

公开(公告)号：FR2835652B1

公开(公告)日：2005-04-15

申请号：FR0201305

申请日：2002-02-04

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  CHANTRE ALAIN

IPC: H01L21/8249

Abstract: When the fabrication of the insulated gate field effect transistor is started, then the bipolar transistor (BIP1,BIP2) is totally fabricated, before the resumption of fabrication of the insulated gate field effect transistor (MOS), and the step of common finishing of the two transistors is executed, including the common thermal reheating treatment (122) and common silication treatment.

公开(公告)号：FR2822292A1

公开(公告)日：2002-09-20

申请号：FR0103469

申请日：2001-03-14

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  BAUDRY HELENE ,  DUTARTRE DIDIER

IPC: H01L21/331 ,  H01L29/737