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    32.
    发明专利
    未知

    公开(公告)号：FR2856185A1

    公开(公告)日：2004-12-17

    申请号：FR0307050

    申请日：2003-06-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： LECONTE BRUNO ,  CAVALERI PAOLA ,  ZINK SEBASTIEN

    IPC: G11C16/10

    Abstract: The memory has a sequencer (SEQ2) to store sequence of external words in a buffer memory (BMEM2). The sequencer stores internal words present in the page in the buffer memory, erases the page and stores words present in the buffer memory in the erased page. The page is formed by memory cell in a main memory (FMEM2). The buffer memory has the external words and the internal words. An independent claim is also included for a method for storing sequence of external words in a target page of a main memory.

    36.
    发明专利
    未知

    公开(公告)号：FR2799045B1

    公开(公告)日：2002-02-08

    申请号：FR9912150

    申请日：1999-09-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： ZINK SEBASTIEN ,  BERTRAND BERTRAND ,  NAURA DAVID

    IPC: G11C16/06 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/02

    Abstract: The integrated circuit memory is of EEPROM type, comprising the data input (D1) and the data output (DO), a planar memory (MM) organized inn words memory (M0-M7), a set of columns registers (LAT) associated with words memory, the first means regarding the write operation for loading the binary data of binary word received at the data input directly to latches (HV0-HV7) of columns register associated with the words memory, and the second means regarding the read operation for a successive reading of binary data stored in the memory cells of words memory and a direct delivery of each binary data in serial form to the data output. The latches for storage and switching (HV0-HV7) comprise each two inverters in antiparallel connection for the storage of binary datum in the form of higher programming voltage or the zero voltage, coupled to the means for conditional switching in the form of two transistors connected in series for carrying the higher programming voltage to the determined bit line, and the loading means in the form of two transistors with the common source connection. The first and second means also comprise the means for an application of selection signals (Bit0-Bit7) to the loading means of latches of each columns register, and the means for loading the data into latches which act via the register selection means in the form of a transistor common to all the latches of the determined columns register. The means for the loading data into latches are common to all columns registers of the memory. The second means comprise a single read line, READLINE, connecting the set of columns registers (LAT) to a read circuit, SENSEAMP. The read circuit comprises only one read amplifier to detect a current flowing in the read line. The memory comprises only one output data line, OUTPUTDATALINE, connecting the output of read circuit to the data output (DO) via a buffer circuit, OUTBUF. The first means comprise only one input data line, INPUTDATALINE, connecting the data input (DI) to the set of columns registers (LAT) via a buffer circuit, INBUF.

    Serial memory of electrically erasable and programmable read-only type with advanced data reading, for use in computing
    37.
    发明专利
    Serial memory of electrically erasable and programmable read-only type with advanced data reading, for use in computing 未知

    公开(公告)号：FR2805653A1

    公开(公告)日：2001-08-31

    申请号：FR0002449

    申请日：2000-02-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAVALERI PAOLA ,  LECONTE BRUNO ,  ZINK SEBASTIEN

    IPC: G11C7/10 ,  G11C8/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C7/00 ,  G11C16/02

    Abstract: The memory in the form of an integrated circuit (MEM1) has an input (DIN) and an output (DOUT) in series and comprises means including a multiplexer (MEX1) for data reading on the reception of a partial address (ADR1) wherein N low-value bits are missing with respect to a complete address. The advanced reading operation comprises the following steps: the simultaneous reading of P first bits, that is P1(W0), P1(W1), ..., P1(WM), of M binary words (W0,W1,...WM) of the memory with the same partial address, when the received address is complete, that is comprising (ADR1,ADR2), the selection of P first bits of word indicated by the complete address and the delivery of these bits to the output, and the reading of subsequent P bits of word indicated by the complete address during the delivery of P preceding bits, and the delivery of the subsequent bits to the output when the preceding bits are delivered. The reading of P subsequent bits is effected like the reading of first P bits, that is by simultaneous reading of subsequent bits of words having the same partial address, and the selection of subsequent bits of word indicated by the complete address. The reading operation is effected by applying the partial address to a decoder and by scanning the low-value address inputs allowing for 2N possible combinations of N low-value bits (A0,A1,...AN-1). A memory unit comprising cells laid out according to word lines and bit lines, where the bit lines are laid out in columns, also comprises an address decoder for the simultaneous selection of P bit lines of M columns, and an interconnection bus for connecting the selected bit lines to the reading circuits, that is sense amplifiers. A memory unit comprises cells laid out according to word lines and bit lines, where a word line forms a page memory, and the reading operation comprises a preliminary step which includes the registering of M words of the same partial address in M adjacent sub-pages, of each word in P adjacent sets of cells, each comprising K/P adjacent subsets of cells, where K is the number of bits of each word, and of bits of rank j and j+1 of word in sets of adjacent cells, and of rank j and j+P of word in subsets of adjacent cells, so that the words are folded in the sub-pages. The number P is equal to K/M where M is equal to 2N; in particular, N = 1, and M = 2. The P first bits of each word are high-value bits. The address decoder comprises transistors for the selection of bit lines, a programming circuit comprising M times K latches connected to the input of data bus having K leads, and also the means for the inhibition of N low-value address inputs in reading mode. A multiplexer in memory unit with subsets of cells is controlled by a scanning circuit. A memory unit comprising a block memory and peripheral elements, also comprises the means for interlacing bits in the form of random-access memory positioned between the data input and the block input, to form composite words comprising M sets of P bits of M different binary words. The memory also comprises means for registering composite words in a buffer memory.

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