公开(公告)号：ITVA20020034A1

公开(公告)日：2003-11-17

申请号：ITVA20020034

申请日：2002-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： AIELLO NATALE ,  PATTI DAVIDE

IPC: H01L27/06 ,  H01L29/94

Abstract: A capacitor for sensing the substrate voltage is efficiently and economically realized simply by isolating a portion or segment of the metal layer that normally covers the heavily doped perimetral region of electric field equalization and, in correspondence of such a metal segment isolated by the remaining portion, by not removing preventively the isolation dielectric layer of silicon oxide from the surface of the semiconductor substrate, as it is normally done on the remaining portion of the perimetral edge region before depositing the metal. The unremoved layer of isolated silicon oxide (12) becomes the dielectric layer of the so constituted capacitor, a plate of which is the heavily doped perimetral region (4) that is electrically connected to the substrate (drain or collector region) while the other plate is constituted by the segment of metal (4'), isolated from the remaining metal layer defined directly over the heavily doped perimetral region (4).

公开(公告)号：DE69902877D1

公开(公告)日：2002-10-17

申请号：DE69902877

申请日：1999-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： AIELLO NATALE

IPC: H01L21/761 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082

Abstract: An integrated circuit structure of the type formed on a semiconductor substrate (5) with conductivity of a first type (N), comprising a first circuit portion (2) incorporated into a first well (6) and including at least one power transistor, and a second control circuit portion (3) incorporated into a second well (7), and comprising an intermediate region (4) located between said first and second circuit portions, the first well (6), second well (7) and intermediate region (4) having conductivity of a second type (P). The integrated circuit structure according to the invention comprises a circuit means of biasing the intermediate region (4) at a value of potential which is tied to the value of potential of the first well (6), thereby cutting off a flow of parasitic current from the wells (6,7) to the semiconductor substrate (5).

公开(公告)号：ITTO20010219A1

公开(公告)日：2002-09-09

申请号：ITTO20010219

申请日：2001-03-09

Applicant: ST MICROELECTRONICS SRL

Inventor： AIELLO NATALE ,  GENNARO FRANCESCO GIOVANNI

IPC: H02M3/155

Abstract: The converter uses the energy stored in the output filter of a step-down (or buck) converter and in the inductor of a step up/down (or buck-boost) converter to supply a second output of opposite sign. In particular, the converter has a first input receiving an input voltage; a first output supplying a first output voltage of a first sign; a second output supplying a second output voltage of opposite sign; a controlled switch connected between the first input and a first intermediate node; an inductor connected between the first intermediate node and the first output; a diode connected between the first intermediate node and a second intermediate node; and a dual voltage generating circuit connected between the second intermediate node and the second output.

公开(公告)号：ITMI20002125A1

公开(公告)日：2002-04-02

申请号：ITMI20002125

申请日：2000-10-02

Applicant: ST MICROELECTRONICS SRL

Inventor： AIELLO NATALE ,  LA BARBERA ATANASIO ,  RANDAZZO VINCENZO ,  TORRISI GIOVANNI LUCA

IPC: H05B41/285

Abstract: An electronic thermal protection circuit is for high currents which can occur in the start-up phase in lighting converters. The circuit is associated with a power device having an output terminal connected to an electric load and at least one control terminal receiving a predetermined driving current value by a driving circuit portion. Advantageously, an integrated temperature sensor is provided to detect the temperature of the power device, and an output stage is connected downstream of the sensor to switch off the driving circuit portion when a predetermined operation temperature is exceeded.

公开(公告)号：DE69325027T2

公开(公告)日：1999-09-16

申请号：DE69325027

申请日：1993-12-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： SCACCIANOCE SALVATORE ,  PALARA SERGIO ,  AIELLO NATALE

IPC: G05F3/30

Abstract: A bandgap voltage reference circuit employs a Vbe voltage multiplier network in a feedback line of an output amplifier of the bandgap reference circuit, thus permitting to independently fix the output voltage that is produced and the temperature coefficient thereof. A voltage reference having a linear negative temperature coefficient in an extended temperature variation range may be obtained, starting from a bandgap reference voltage with a positive temperature coefficient.

公开(公告)号：DE69325027D1

公开(公告)日：1999-06-24

申请号：DE69325027

申请日：1993-12-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： SCACCIANOCE SALVATORE ,  PALARA SERGIO ,  AIELLO NATALE

IPC: G05F3/30

Abstract: A bandgap voltage reference circuit employs a Vbe voltage multiplier network in a feedback line of an output amplifier of the bandgap reference circuit, thus permitting to independently fix the output voltage that is produced and the temperature coefficient thereof. A voltage reference having a linear negative temperature coefficient in an extended temperature variation range may be obtained, starting from a bandgap reference voltage with a positive temperature coefficient.

公开(公告)号：DE69128936D1

公开(公告)日：1998-03-26

申请号：DE69128936

申请日：1991-11-25

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  AIELLO NATALE

IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219 ,  H01L21/76

Abstract: The structure comprises at least arms (1, 2) each formed from a first and a second MOS transistor (M3, M1; M4, M2). Its integrated monolithic construction provides for a type N++ substrate (3) forming a positive potential output terminal (K1) which is overlaid by a type N-epitaxial layer (4). For each of the first transistors (M3; M4) this comprises a type P, P+ insulating region (13, 25; 14, 26) containing a type N+ enriched drain region (15; 16), a type N drain region (19; 20) and, in succession, a type P body region (21; 22) and a pair of type N+ source regions (23; 24) forming a negative potential output terminal (A1) respectively. For each of the second transistors (M1, M2) the structure comprises a type N+ enriched drain region (5, 6) containing a type N drain region (31, 32) and in succession a type P body region (9; 10) and a pair of type N+ regions (11; 12) forming corresponding alternating current inputs (A3, A4) respectively.