公开(公告)号：DE69128494T2

公开(公告)日：1998-04-16

申请号：DE69128494

申请日：1991-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.

公开(公告)号：IT1240012B

公开(公告)日：1993-11-27

申请号：IT2015790

申请日：1990-04-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175 ,  H03K

Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.