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    FLASH EEPROM MEMORY ARRAY AND BIASING METHOD THEREFOR
    2.
    发明专利
    FLASH EEPROM MEMORY ARRAY AND BIASING METHOD THEREFOR 失效

    公开(公告)号：JPH0855921A

    公开(公告)日：1996-02-27

    申请号：JP9322995

    申请日：1995-03-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DALLABORA MARCO ,  SALI MAURO LUIGI ,  TASSAN CASER FABIO ,  VILLA CORRADO

    IPC: H01L21/8247 ,  G11C16/04 ,  G11C16/16 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PURPOSE: To provide a NOR flash type memory array corresponding to the programming of small current without changing any auxiliary element such a decode, sense and load devices. CONSTITUTION: Concerning a flash EEPROM memory array 35, asymmetric structure is provided by memory cells 36 having source areas composed of row/column style and connected to respective bit lines BL, source regions connected to common source lines BLS and control gate regions connected to respective work lines WL and in that asymmetric structure, either the source region or the drain region provides a high resistant section so that the cells in various areas can be programmed and erased. The memory array 35 includes a bias transistor 41 for preventing spurious writing by keeping the drain region and source region of cell connected to the bit line, to which any address is not designated, at the same potential when programming.

    CMOS LOGIC CIRCUIT IN BUFFER-TYPE DATA OUTPUT STAGE
    4.
    发明专利
    CMOS LOGIC CIRCUIT IN BUFFER-TYPE DATA OUTPUT STAGE 失效

    公开(公告)号：JPH05102825A

    公开(公告)日：1993-04-23

    申请号：JP12301991

    申请日：1991-04-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

    IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

    Abstract: PURPOSE: To reduce noise at an output terminal by lowering a peak current at the time of switching operation in a CMOS logic circuit being a buffer-type data output stage having a 1st feedback loop and a 2nd feedback loop. CONSTITUTION: This buffer-type data output stage CMOS logic circuit is composed of the 1st and the 2nd feedback loops 8 and 9 having a mutually independent configuration respectively, connected between a common output node 3 and each gate electrode of corresponding transistors M1 and M2, and precharging the output node 3 at a prescribed voltage value. The 1st feedback loop 8 is operated in a logic H of the output node 3, and the 2nd feedback loop 9 is operated at the time of a logic L, to precharge the output node 3, the peak current in a switching period is lowered, and the noise in the switching period is reduced.

    GENERATING METHOD OF REFERENCE SIGNAL FOR EVALUATING DIFFERENCE OF CONTENT OF NONVOLATILE MEMORY CELL AND GENERATING CIRCUIT THEREOF
    5.
    发明专利
    GENERATING METHOD OF REFERENCE SIGNAL FOR EVALUATING DIFFERENCE OF CONTENT OF NONVOLATILE MEMORY CELL AND GENERATING CIRCUIT THEREOF 失效

    公开(公告)号：JPH0855486A

    公开(公告)日：1996-02-27

    申请号：JP6942595

    申请日：1995-03-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  DALLABORA MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34

    Abstract: PURPOSE: To maintain the precision of a virgin cell for a long period and improve the reliability of the circuit by using the virgin cell which has characteristics shifted by a voltage shifter. CONSTITUTION: A cell and virgin cells 12 and 13 have gate-source voltages lower than a source voltage through voltage shifters 14 and 15 and their characteristics depend upon an operating load. In read mode, a logical signal R is low and a logical signal V is high, so switches 21, 26, 29, 33, and 40 are closed and a switch 42 is opened. When the source voltage is lower than 2.3V as the threshold voltage of the cells 12 and 13, the cells 11, 12, and 13 are turned off. When the source voltage exceeds it, the cells 12 and 13 turn on, but their characteristics become smaller than a logical slope because of the presence of the load. The cell 11 is off between 2.3V and the source voltage and then a current flows to neither a load transistor 18 nor a mirror transistor 23; and only the cell 12 has a high resistance value and a current is made to flow through a load transistor 30 for supply current limitation.

    BIASING METHOD FOR NONVOLATILE FLASH EEPROM MEMORY ARRAY
    6.
    发明专利
    BIASING METHOD FOR NONVOLATILE FLASH EEPROM MEMORY ARRAY 失效

    公开(公告)号：JPH0750398A

    公开(公告)日：1995-02-21

    申请号：JP4720994

    申请日：1994-03-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115

    Abstract: PURPOSE: To prevent the occurrences of stress in the drain terminal of an unselected memory cell in a selected bit line by biasing a positive voltage with respect to the drain terminal of the unselected memory cell for a substrate region and by making the source terminal remain floating. CONSTITUTION: This memory array is provided with a drain region 29 arranged into rows and columns and connected to each of bit lines BL, a source region 30 connected to each source line 24, a control gate region connected to each word line WL, and a large number of memory cells 21 each having a substrate region 28 housing the drain and source regions. A drain terminal of an unselected memory cell, which is connected to a selected bit line during a reading step but not connected to the selected word line and is not connected to the source terminal of the selected memory cell, is biased with a positive voltage with respect to the substrate region 28. The source terminal is kept floating.

    9.
    发明专利
    未知

    公开(公告)号：DE69325442T2

    公开(公告)日：1999-12-16

    申请号：DE69325442

    申请日：1993-03-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: To reduce the number of depleted cells (21) and the errors caused thereby, the memory array (20) comprises a number of groups of control transistors (23) relative to respective groups (22) of memory cells. The control transistors (23) of each group are NMOS transistors having the drain terminal connected to its own control line (BLP), and each of the control transistors of one group is relative to a row portion of the memory array (20): More specifically, each control transistor (23) presents the control gate connected to the respective word line (WL), and the source region connected to the source region of the cells (21) in the same row and in the same group (22).

    10.
    发明专利
    未知

    公开(公告)号：DE69128494D1

    公开(公告)日：1998-02-05

    申请号：DE69128494

    申请日：1991-04-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

    IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

    Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.

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