公开(公告)号：JPH05102825A

公开(公告)日：1993-04-23

申请号：JP12301991

申请日：1991-04-26

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

Abstract: PURPOSE: To reduce noise at an output terminal by lowering a peak current at the time of switching operation in a CMOS logic circuit being a buffer-type data output stage having a 1st feedback loop and a 2nd feedback loop. CONSTITUTION: This buffer-type data output stage CMOS logic circuit is composed of the 1st and the 2nd feedback loops 8 and 9 having a mutually independent configuration respectively, connected between a common output node 3 and each gate electrode of corresponding transistors M1 and M2, and precharging the output node 3 at a prescribed voltage value. The 1st feedback loop 8 is operated in a logic H of the output node 3, and the 2nd feedback loop 9 is operated at the time of a logic L, to precharge the output node 3, the peak current in a switching period is lowered, and the noise in the switching period is reduced.

公开(公告)号：EP0455002B1

公开(公告)日：1997-12-29

申请号：EP91105323

申请日：1991-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00361

公开(公告)号：DE69128494D1

公开(公告)日：1998-02-05

申请号：DE69128494

申请日：1991-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.

公开(公告)号：DE69128494T2

公开(公告)日：1998-04-16

申请号：DE69128494

申请日：1991-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.

公开(公告)号：IT1240012B

公开(公告)日：1993-11-27

申请号：IT2015790

申请日：1990-04-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175 ,  H03K

Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.