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    31.
    发明专利
    未知

    公开(公告)号：ES2120974T3

    公开(公告)日：1998-11-16

    申请号：ES92112639

    申请日：1992-07-23

    Applicant: ST MICROELECTRONICS SRL ,  MAGNETI MARELLI SPA

    Inventor： MAZZUCCO MICHELANGELO ,  POLETTO VANNI ,  MORELLI MARCO

    IPC: G01N27/409 ,  H03F3/45

    Abstract: In order to achieve a high input dynamic range as well as high CMRR and PSRR values and input impedance with the use of a single supply voltage (Vcc), the amplifier includes an input stage with two transistors (Q1, Q2) which are biased by a constant current (IP3, IP4), preferably of less than 1 microampere, and the collectors of the transistors (Q1, Q2) are kept at fixed reference voltages (VR1, VR2). The input signal (VIN) applied between the emitters (IN(-), IN(+)) of the transistors (Q1, Q2) is transferred to the terminals of a first resistor (R1) which is supplied with current (IR1) from a circuit (M7, A5, R3; M10, Q6, R4; M9, Q7, R5) which mirrors the current (IR1) into a second resistor (R6), from the terminals of which the output signal (VOUT) is taken. The preferred application is for forming interfaces for lambda probes fitted to catalytic converters for motor vehicles.

    32.
    发明专利
    未知

    公开(公告)号：DE69227244D1

    公开(公告)日：1998-11-12

    申请号：DE69227244

    申请日：1992-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： POLETTO VANNI ,  MORELLI MARCO

    IPC: H01L29/73 ,  G05F1/569 ,  H01L21/331 ,  H03K17/0422 ,  G05F1/56 ,  H03K17/04

    Abstract: Saturation of a bipolar power transistor is controlled by sensing the current which is eventually injected into the substrate of the integrated circuit by the saturating transistor and using this signal for exerting a limiting action on the current which is driven to the base of the power transistor by a dedicated driving circuit. Differently from the prior art antisaturation systems, it is no longer necessary to precisely monitor the operating voltages across the terminals of the bipolar power transistor. A suitable sensing resistance may be integrated conveniently at a distance from the often complex integrated structure of the bipolar transistor. The system of the invention offers numerous advantages and ensures intervention of the antisaturation circuit only when the power transistor has positively reached a state of saturation, but well before any unwanted consequence.

    33.
    发明专利
    未知

    公开(公告)号：IT1251205B

    公开(公告)日：1995-05-04

    申请号：ITTO910707

    申请日：1991-09-18

    Applicant: ST MICROELECTRONICS SRL ,  MARELLI AUTRONICA

    Inventor： POLETTO VANNI ,  MORELLI MARCO ,  POMA ALBERTO

    IPC: H03K17/08 ,  H02M1/00 ,  H02M1/38 ,  H03K17/082 ,  H03K17/66 ,  H03K

    Abstract: The circuit includes two output terminals (OUT1, OUT2) for connection to the terminals of a load (L), first and second pairs of electronic power switches (Q1, Q4; Q2, Q3) which are connected between the output terminals (OUT1, OUT2) and the two poles of a direct-current voltage supply (Vs) so as to form an H-shaped structure with the load (L), and a driver circuit (C1, C2) for selectively making the electronic power switches of the first pair (Q1, Q4) of the second pair (Q2, Q3) order to cause a current to flow through the load (L) in one direction or the other respectively, and for preventing the electronic switches (Q1, Q3; Q2, Q4) which are connected between the same output terminal (OUT1; OUT2) and the two poles of the voltage supply (Vs) from conducting simultaneously.

    Eine Treiberschaltung, entsprechendes Bauelement, Vorrichtung und Verfahren
    34.
    发明专利
    Eine Treiberschaltung, entsprechendes Bauelement, Vorrichtung und Verfahren 未知

    公开(公告)号：DE102017113530B4

    公开(公告)日：2022-06-15

    申请号：DE102017113530

    申请日：2017-06-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： POLETTO VANNI ,  PROVINZANO BIAGIO

    IPC: H03F3/45

    Abstract: Schaltung (100), umfassend:- einen ersten (Gxy) und einen zweiten (Sxy) Ausgangsanschluss, die mit einem Leistungstransistor (T) koppelbar sind,- eine Differenzstufe (10), die einen nicht invertierenden und einen invertierenden Eingang aufweist, zum Aufnehmen einer Eingangsspannung (Vin), die über dem nicht invertierenden und dem invertierenden Eingang angelegt ist, wobei die Eingangsspannung (Vin) als eine Ausgangsspannung (Vgs) über dem ersten (Gxy) und dem zweiten (Sxy) Ausgangsanschluss repliziert wird, um ein Treibersignal für den Leistungstransistor bereitzustellen, wobei die Differenzstufe (10) einen Differenz-Transkonduktanz-Verstärker (M7, M8) in einer Spannungsfolgeranordnung beinhaltet, die kontinuierliche Regelung der Spannung an dem ersten Ausgangsanschluss (Gxy) relativ zu dem zweiten Ausgangsanschluss (Sxy) vorsieht, dadurch gekennzeichnet, dass die Differenzstufe (10) eine Spannungsklemme (D1, D2, D3; T1, T2, D2, D3) zum Klemmen der Ausgangsspannung (Vgs) über dem ersten (Gxy) und dem zweiten (Sxy) Ausgangsanschluss auf einen Spitzenwert beinhaltet, wobei die Spannungsklemme zwischen den zweiten Ausgangsanschluss (Sxy) und eine Versorgungsleitung (CP) zur Schaltung gesetzt ist, und wobei die Spannungsklemme (D1, D2, D3; T1, T2, D2, D3) eine oder mehrere Zener-Dioden (D1, D2, D3) umfasst, die in Serie mit einer kaskadierten Anordnung von zwei Bipolartransistoren (T1, T2) gekoppelt sind.

    37.
    发明专利
    未知

    公开(公告)号：DE60223649T2

    公开(公告)日：2008-10-30

    申请号：DE60223649

    申请日：2002-03-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： POLETTO VANNI ,  GHIGINI PAOLO

    IPC: H04L25/49 ,  H03M5/12 ,  H03M5/14

    Abstract: Method and decoder for decoding a Manchester encoded binary data signal (RX_DATA). The decoding method comprises the following steps: receiving the binary data signal (RX_DATA) comprising a first sequence of bit central transitions (40) and a second sequence of bit initial transitions (42), generating a local clock signal (CK), and determining the central transitions (40) of said encoded binary data signal (RX_DATA), and is characterized in that the central transition (40) determination step comprises the following steps: measuring, by means of the local clock signal (CK), the time interval elapsing between a pair adjacent central transitions (40), expressed as a number N of cycles of the local clock signal (CK), selecting each successive central transition (40) on the basis of the time interval N measured between the pair of central transitions (40) which immediately precede said successive central transition (40).

    40.
    发明专利
    未知

    公开(公告)号：DE69428884D1

    公开(公告)日：2001-12-06

    申请号：DE69428884

    申请日：1994-03-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COLANDREA FRANCESCO ,  POLETTO VANNI

    IPC: H03K17/08 ,  H03K17/082 ,  H03K17/567 ,  H03K17/687

    Abstract: The circuit (10) includes two regulating loops connected parallel to each other. The slow regulating loop (11) presents a lower first intervention threshold, and the fast regulating loop (12) a higher second intervention threshold. The slow regulating loop is low-gain and frequency-stable for accurately controlling the maximum value of the current (ID) supplied by the driver (1) in the event of slow overloads or transient states. In the event of rapid overloads, the slow regulating loop fails to intervene effectively, current supply increases rapidly, and the fast regulating loop is turned on to rapidly discharge the parasitic capacitance of the driver (1). The resulting increase in current supply due to instability of the fast loop poses no hazard by virtue of the power transistor being saturated and so permitting effective intervention of the slow regulating loop (linear regulating region) which maintains the output current at the set nominal value.

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