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    Row selector for a semiconductor memory device built from low voltage transistors
    31.
    发明公开
    Row selector for a semiconductor memory device built from low voltage transistors 有权
    Zeilenselektorfüreinen Halbleiterspeicher mit Niedrigspannungstransistoren

    公开(公告)号：EP1837880A1

    公开(公告)日：2007-09-26

    申请号：EP06113480.5

    申请日：2006-05-04

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C8/08 ,  G11C16/12

    CPC classification number: A61K31/737 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  H01L27/0266 ,  H03K17/005 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/675

    Abstract: A row selector for a semiconductor memory including a plurality of memory cells coupled to a corresponding plurality of word lines, the row selector comprising, for each word line: a first biasing circuit path (230;215;260) adapted to bias the corresponding word line to a programming voltage when said corresponding word line is selected for selectively performing a program operation on at least one memory cell coupled to the corresponding word line, the first biasing circuit path comprising programming voltage provisioning means (215) adapted to provide the programming voltage; a second biasing circuit path (235) which is adapted to receive, from program-inhibit voltage provisioning means (250) a program inhibit voltage (GND), and to provide to the corresponding word line said program inhibit voltage (GND) when the word line is unselected during the program operation, first biasing means (220,225) for driving the second biasing circuit path in order to control a conduction state thereof; wherein: said first biasing circuit path includes a first transistor (M2) controlled to be electrically conductive when the corresponding word line is selected, and to be electrically non-conductive when the corresponding word line is unselected; said first biasing means controls the second biasing circuit path to be conductive when, during the program operation, the corresponding word line is unselected, said second biasing circuit path includes a plurality of series connected transistors, a number of transistors in said plurality being at least equal to the smallest integer not less than an absolute value of a ratio between a voltage equal to the difference between the programming voltage and the program-inhibit voltage to a predetermined maximum voltage given by the maximum voltage which a transistor of said series-connected transistors can sustain before it breaks down.

    Abstract translation: 一种用于半导体存储器的行选择器，包括耦合到对应的多个字线的多个存储器单元，所述行选择器包括：对于每个字线：适于偏置相应字词的第一偏置电路路径（230; 215; 260） 当选择所述对应的字线用于在耦合到对应字线的至少一个存储单元上选择性地执行编程操作时，所述第一偏置电路路径包括编程电压提供装置（215），其适于提供编程电压 ; 第二偏置电路路径（235），其适于从编程禁止电压供应装置（250）接收编程禁止电压（GND），并且在所述字处理时向所述对应字线提供所述编程禁止电压（GND） 在程序操作期间，线路未选择，用于驱动第二偏置电路路径的第一偏置装置（220,225），以便控制其导通状态; 其中：所述第一偏置电路路径包括当选择相应的字线时被控制为导电的第一晶体管（M2），并且当相应的字线未被选择时是不导电的; 当编程操作期间相应的字线未选择时，所述第一偏置装置控制第二偏置电路路径导通，所述第二偏置电路路径包括多个串联连接的晶体管，所述多个晶体管中的多个晶体管至少为 等于最小整数，其不小于等于编程电压与编程禁止电压之差的电压与由所述串联晶体管的晶体管的最大电压给定的预定最大电压之间的比率的绝对值 在它崩溃之前可以维持。

    Single cell erasing method for recovering cells under programming disturbs in non volatile semiconductor memory devices
    34.
    发明公开
    Single cell erasing method for recovering cells under programming disturbs in non volatile semiconductor memory devices 有权
    EinzelzelllöschverfahrenderRückgewinnungvonprogammiergestörteZellen innichtflüchtigeSpeichervorrichtung

    公开(公告)号：EP1424700A1

    公开(公告)日：2004-06-02

    申请号：EP02425727.1

    申请日：2002-11-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Camerlenghi, Emilio ,  Campardo, Giovanni ,  Ghilardi, Tecla

    IPC: G11C16/34

    CPC classification number: G11C16/3431 ,  G11C16/3404 ,  G11C16/3418

    Abstract: The present invention relates to a particular single cell erasing method for recovering memory cells under reading or programming disturbs in non volatile semiconductor memory electronic devices comprising cell matrix split in sectors and organised in rows, or word lines, and columns, or bit lines.
    This kind of memory devices generally provides the application of a sector erasing algorithm with subsequent testing phase (erase-verify); but the method according to the present invention provides a bit by bit erasing by applying to each single word line a negative voltage used during the erasing of a whole sector and on the drain terminal of each single cell a programming voltage.
    With this kind of selective bias it is possible to perform a single cell, or bit by bit, erasing, allowing all the cells in case under a reading or programming disturb increasing the original threshold value thereof to be recovered.

    Abstract translation: 本发明涉及一种用于在非易失性半导体存储器电子设备中读取或编程干扰下的存储器单元的特定单元擦除方法，所述非易失性半导体存储器电子器件包括扇区中的单元矩阵分割并且以行或字线，列或位线组织。 这种存储器件通常提供具有随后的测试阶段（擦除验证）的扇区擦除算法的应用; 但是根据本发明的方法通过在每个单个字线上施加在擦除整个扇区期间使用的负电压并且在每个单个电池的漏极端子上施加编程电压来逐位擦除。 利用这种选择性偏置，可以执行单个单元或逐位擦除，从而允许在读取或编程干扰的情况下的所有单元增加其要恢复的原始阈值。

    Method for detecting a resistive path or a predeterminted potential in non-volatile memory electronic devices
    36.
    发明公开
    Method for detecting a resistive path or a predeterminted potential in non-volatile memory electronic devices 有权
    的电子非易失性存储器装置检测的电阻路径或者预定电势的方法，

    公开(公告)号：EP1403880A1

    公开(公告)日：2004-03-31

    申请号：EP02425593.7

    申请日：2002-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C29/00

    CPC classification number: G11C29/82 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008 ,  G11C29/83 ,  G11C29/832

    Abstract: The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells (4) arranged in rows and columns, with at least one row-decoding circuit portion per sector (20) being supplied positive and negative voltages (Vpcx, HVNEG).
    This method becomes operative upon a negative erase algorithm issue, and comprises the following steps:

    forcing the read condition of a sector (20) that has not been completely erased;
    scanning the rows of said sector (20) to check for the presence of a spurious current indicating a failed state;
    finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector (20).

    Abstract translation: 该方法包括迫使读取条件到任何完全擦除扇区。 该部门的行进行扫描来检查当前虚假的可能存在，表明所有这一切是一个失败的国家。 流过一排寄生电流被发现，所有这一切都被电通过重新寻址的行，以相同的扇区提供一个冗余行隔离。 因此独立claimsoft被包括用于在可编程和电可擦除型的集成的非易失性存储器设备。

    Method and circuit for generating reference voltages for reading a multilevel memory cell
    40.
    发明公开
    Method and circuit for generating reference voltages for reading a multilevel memory cell 有权
    操作和电路，用于产生参考电压，用于读取的多值存储单元

    公开(公告)号：EP1253597A1

    公开(公告)日：2002-10-30

    申请号：EP01830276.0

    申请日：2001-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C11/56 ,  G11C5/14

    CPC classification number: G11C11/56 ,  G11C5/147 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5634

    Abstract: The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell (236) and a second memory cell (236) respectively having a first reference programming level and a second reference programming level; a first reference circuit (46) and a second reference circuit (47) respectively connected to said first and said second memory cells (236) and having respective output terminals (60) which respectively supply a first reference voltage (VR1) and a second reference voltage (VRN-1); and a voltage divider (48) having a first connection node (42.1) and a second connection node (42.N-1) respectively connected to the output terminals (60) of the first reference circuit (46) and of the second reference circuit (47) to receive, respectively, the first reference voltage (VR1) and the second reference voltage (VRN-1), and a plurality of intermediate nodes (42.2,..., 42.N-2) supplying respective third reference voltages (VR2,..., VRN-2) at equal distances apart.

    Abstract translation: 用于产生参考电压，用于读取多电平存储器单元中的电路包括以下内容：分别具有第一参考电平的编程和第二参考电平编程第一存储器单元（236）和一个第二存储单元（236）; 其分别提供第一参考电压的第一参考电路（46）和第二参考电路（47）分别连接到所述第一和所述第二存储器单元（236）和具有respectivement输出端子（60）（VR1）和第二参考 电压（VRN-1）; 并分别连接到所述第一参考电路（46）的输出端子（60）的分压器（48），其具有第一连接节点（42.1）和第二连接节点（42.n-1）和第二参考电路的 （47），以分别接收所述第一参考电压（VR1）和第二参考电压（VRN-1），和中间节点的多个（42.2，...，42.n-2）供给respectivement第三参考电压 （VR2，...，VRN-2）相等的距离隔开。

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