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    Method for refreshing stored data in an electrically erasable and programmable non-volatile memory
    31.
    发明公开
    Method for refreshing stored data in an electrically erasable and programmable non-volatile memory 有权
    过程用于刷新存储在电可擦除和可编程的非易失性存储器中的数据

    公开(公告)号：EP1233421A1

    公开(公告)日：2002-08-21

    申请号：EP01830110.1

    申请日：2001-02-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico

    IPC: G11C16/34

    CPC classification number: G11C16/3418

    Abstract: Method for refreshing data stored in an electrically erasable and programmable non-volatile semiconductor memory comprising at least one two-dimensional array (1) of memory cells (MC) containing a plurality of individually erasable and programmable memory pages (R). Each time a request to modify a content of a memory page is received by the memory, the method provides for modifying (201;502;602) the content of said memory page and submitting a portion (S1-SZ;R) of the two-dimensional array to a refresh procedure (202-208;501,503-509;601,603-612). The refresh procedure comprises detecting (203;505;606) memory cells of that memory portion that have partially lost a respective datum stored therein and reprogramming the datum in the detected memory cells.

    Abstract translation: 对于存储在电可擦除和可编程的非易失性半导体存储器，包括存储单元（MC）包含单独可擦除和可编程存储器页（R）的多个的至少一个二维阵列（1）刷新数据的方法。 每个时间的请求来修改存储器页的内容由存储器接收，该方法提供了用于修饰（201; 502; 602）所述存储器页的内容和提交的部分（S1-SZ; R）两者的 维阵列的刷新程序（202-208; 501.503至509; 601.603到612）。 （203; 505; 606）的刷新程序包括：检测存储器部分中的存储单元并thathave部分失去一个respectivement日期所存和重新编程在检测到的存储器单元的时间。

    Enhancing protection of dielectrics from plasma induced damages
    32.
    发明公开
    Enhancing protection of dielectrics from plasma induced damages 审中-公开
    Beschädigung的Verbesserter Schutz von Dielektrika vor plasmainduzierter

    公开(公告)号：EP1006568A1

    公开(公告)日：2000-06-07

    申请号：EP98830722.9

    申请日：1998-12-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico

    IPC: H01L21/311 ,  H01L21/3213

    CPC classification number: H01L21/31116 ,  H01L21/32136

    Abstract: During critical plasma etching steps, the wafer's surface is illuminated with electromagnetic radiation in the visible and/or in UV spectrum of energy and power density sufficient to enhance the reverse current through protective junctions that are commonly realized for providing electrical discharge paths for electrical charges picked up by exposed conductive parts to limit the level of induced voltages to values compatible with the preservation of the integrity of functional dielectric layers coupled to the exposed conductors parts and to the semiconductor substrate or to another conductive part.

    Abstract translation: 在临界等离子体蚀刻步骤期间，晶片的表面以能量和/或紫外光谱中的电磁辐射被照射，能量和功率密度足以增强通过保护结的反向电流，这通常被实现为提供用于选择的电荷的放电路径 通过暴露的导电部件将感应电压的电平限制为与保持耦合到暴露的导体部分和半导体衬底或另一个导电部分的功能电介质层的完整性兼容的值。

    Improved field-effect transistor and corresponding manufacturing method
    33.
    发明公开
    Improved field-effect transistor and corresponding manufacturing method 审中-公开
    Verbesserter Feldeffekttransistor和Verfahren zu dessen Herstellung

    公开(公告)号：EP1003222A1

    公开(公告)日：2000-05-24

    申请号：EP98830694.0

    申请日：1998-11-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico ,  Zuliani, Paola

    IPC: H01L29/10 ,  H01L21/336 ,  H01L21/266

    CPC classification number: H01L29/1041 ,  H01L21/76202

    Abstract: Field effect transistor (1) integrated on a semiconductor substrate (4) with a respective active area (8) comprising:

    a region of source (2) and a region of drain (3) formed in the semiconductor substrate (4),
    a channel region (5) interposed between said regions of source (2) and of drain (3) having a predefined nominal width (W N ), wherein said channel region (5) has an effective width (Weff) defined by a variable profile of doping.

    Abstract translation: 集成在具有相应有源区域（8）的半导体衬底（4）上的场效应晶体管（1）包括：源极（2）的区域和形成在半导体衬底（4）中的漏极（3）的区域，沟道 位于源极（2）的所述区域和具有预定标称宽度（WN）的漏极（3）的所述区域之间的区域（5），其中所述沟道区域（5）具有由掺杂的可变轮廓限定的有效宽度（Weff）。

    Circuit structure comprising a parasitic transistor having a very high threshold voltage
    34.
    发明公开
    Circuit structure comprising a parasitic transistor having a very high threshold voltage 失效
    Schaltkreis mit einemparasitären晶体管hoher Einsatzspannung

    公开(公告)号：EP0977265A1

    公开(公告)日：2000-02-02

    申请号：EP98830461.4

    申请日：1998-07-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Dalla Libera, Giovanna ,  Pio, Federico

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/49

    CPC classification number: H01L27/088 ,  H01L21/823475

    Abstract: A circuit structure integrated in a semiconductor substrate (40) comprises at least one pair of transistors (20,21) being formed each in a respective active area region (30) and having a source region (22) and a drain region (23), as well as a channel region (24) intervening between the source and drain regions (22,23) and being overlaid by a gate region (25); the gate regions (25) are connected electrically together by an overlying conductive layer (28) and respective contacts (14) wherein the contacts (14) between the gate regions (24) and the conductive layer (28) are formed above the active areas (30).

    Abstract translation: 集成在半导体衬底（40）中的电路结构包括至少一对晶体管（20,21），每个晶体管分别形成在相应的有源区域（30）中并且具有源极区（22）和漏极区（23） ，以及介于源区和漏区（22,23）之间并被栅极区域（25）覆盖的沟道区（24）; 栅极区域（25）通过覆盖的导电层（28）和相应的触点（14）电连接在一起，其中栅极区域（24）和导电层（28）之间的触点（14）形成在有源区域 （30）。

    An electronic structure comprising high and low voltage transistors, and a corresponding manufacturing method
    35.
    发明公开
    An electronic structure comprising high and low voltage transistors, and a corresponding manufacturing method 审中-公开
    电子组件具有高电压和低电压晶体管和它们的制备方法

    公开(公告)号：EP0954029A1

    公开(公告)日：1999-11-03

    申请号：EP98204129.5

    申请日：1998-12-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico ,  Pizzuto, Olivier

    IPC: H01L27/105 ,  H01L21/8239 ,  H01L21/8234

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    Abstract: A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.

    Abstract translation: 集成在一个半导体衬底具有第一导电类型的至少一个包括第一晶体管HV和至少一个第二LV晶体管，各具有一个栅极对应区域的电子设备的结构。 所述第一HV晶体管具有轻掺杂漏极和源极区具有第二导电类型，和所述第二LV晶体管具有与所述第二导电类型的respectivement漏极和源极区域，每个区域包括一个轻掺杂部分毗邻respectivement栅极区和一个 第二部分全部被更重掺杂，并且包括硅化物层。

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    36.
    发明公开
    "Non-volatile memory cell and corresponding manufacturing process". 失效
    Festwertspeicherzelle und deren Herstellungsverfahren

    公开(公告)号：EP0930655A1

    公开(公告)日：1999-07-21

    申请号：EP98201715.4

    申请日：1998-05-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    Abstract: The invention relates to a non-volatile memory cell and a manufacturing process therefor.
    The cell (1,10) is integrated in a semiconductor substrate (2) and comprises:

    a floating gate transistor (3,30) having a first source region (17,170), first drain region (15,150), and gate region (5,50) projecting over the substrate (2) and intervening between the first source and drain regions (17,15;170,150); and
    a selection transistor (4,40) having a second source region (19,190), second drain region (20,200), and respective gate region (23,230), projecting over the substrate (2), between the second source and drain regions (19,20;190,200). The first and second regions are lightly doped and the cell comprises mask elements (31a, 310a).

    Abstract translation: 本发明涉及一种非易失性存储单元及其制造方法。 电池（1,10）集成在半导体衬底（2）中，包括：具有第一源极区（17,170），第一漏极区（15,150）和栅极区（5）的浮栅晶体管（3,30） 50）突出在所述基板（2）上并且介于所述第一源极和漏极区域（17,15; 170,150）之间; 以及在所述第二源极和漏极区域（19）之间具有突出于所述衬底（2）上的第二源极区域（19,190），第二漏极区域（20,200）和相应栅极区域（23,230）的选择晶体管（4,40） ，20; 190200）。 第一和第二区域被轻掺杂，并且电池包括掩模元件（31a，310a）。

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