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    Process for manufacturing an array of cells including selection bipolar junction transistors
    3.
    发明公开
    Process for manufacturing an array of cells including selection bipolar junction transistors 有权
    用于与所述选择晶体管的双极电池装置和相关联的小区布置的制造方法

    公开(公告)号：EP1408549A1

    公开(公告)日：2004-04-14

    申请号：EP02425604.2

    申请日：2002-10-08

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Casagrande, Guilio ,  Gastaldi, Roberto ,  Vendrame, Loris ,  Benvenuti, Augusto ,  Lowrey, Tyler, c/o Ovonyx Inc.

    IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

    CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

    Abstract: A process for manufacturing an array of cells, including: implanting, in a body (10) of semiconductor material of a first conductivity type, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer (21) having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings (27a) with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions (14) of the first conductivity type; implanting second portions of the active area regions through the second openings (27b) with a doping agent of the second conductivity type, thereby forming control contact regions (15) of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components (3), each storage component having a terminal connected to a respective second conduction region (14).

    Abstract translation: 单元的阵列是通过注入第一导电类型，以通过绝缘层的第一开口有源区区域的第一部分的掺杂剂，以形成第二导电区制成; 注入第二导电类型到穿过绝缘层以形成控制接触区域的第二开口的有源区域的区域的第二部分中的掺杂剂; 和在所述主体的顶部上形成存储元件。 单元阵列的制造包括：提供第一导电类型的半导体材料的本体（10）; 植入在身体中，第一导电类型的公共导电区（11）; 形成在所述主体中，公共导电区域上方，有源区的区域的第二导电类型和第一掺杂水平的（12）; 形成，在所述主体的顶部，绝缘层上具有第一和第二开口（27A，27B）; 通过用第一导电类型的掺杂剂的第一开口注入所述有源区区域的第一部分，从而形成在所述有源区区域中的第一导电类型的第二传导区域; 通过注入与所述第二导电类型的掺杂剂的第二孔中的活性区域的区域的第二部分，所述第二导电类型和第二掺杂水平比所述第一掺杂等级高的形成，从而控制接触区域（15）; 并形成存储元件（24）在所述主体的顶部上。 每个控制接触区域形成，与所述第二传导区域和公共传导区，选择双极型晶体管（20）连接在一起。 每个存储组件具有连接到第二respectivement传导区的端子。 它定义，与双极晶体管，所述单元阵列的细胞一起。

    Method and circuit for generating a gate voltage in non-volatile memory devices
    6.
    发明公开
    Method and circuit for generating a gate voltage in non-volatile memory devices 失效
    方法和电路，用于产生用于非易失性存储器阵列的栅极电压

    公开(公告)号：EP0899742A1

    公开(公告)日：1999-03-03

    申请号：EP97830435.0

    申请日：1997-08-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo ,  Gastaldi, Roberto ,  Calligaro, Cristiano

    IPC: G11C11/00 ,  G11C16/06 ,  G11C11/56

    CPC classification number: G11C11/5642 ,  G11C8/14 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/30 ,  G11C29/00 ,  G11C2211/5634

    Abstract: The present invention relates to a circuit for generating a regulated voltage (RV), in particular for gate terminals of non-volatile memory cells of the floating gate type, which comprises a generator circuit (OSC,CHP) adapted to generate an unregulated voltage (VCHP) on its output, a comparator circuit coupled to the output of the generator circuit (OSC,CHP), including a reference element consisting of a non-volatile memory cell (REFC) of the floating gate type and adapted to output an electric error signal (ID) tied to the difference between the unregulated voltage (VCHP) and the threshold voltage of the cell (REFC), and a regulator circuit (CSEL,CBIAS,IVC,DRV,TR) coupled to the output of the comparator circuit and operative to regulate the unregulated voltage (VCHP) based on the value of the electric error signal (ID). Through the present circuit, the regulated voltage (RV) is made programmable and tied to the parameters of the memory cell (REFC).

    Abstract translation: 本发明涉及一种电路，用于产生调节电压（RV），特别是用于浮置栅极型，其包括生成器电路（OSC，CHP）angepasst产生的非易失性存储单元的栅极端子（在未调节的电压 VCHP）在其输出端，耦合到所述发生器电路（OSC，CHP）包括参考元件由...组成的浮栅型的非易失性存储单元（REFC）的和angepasst电动错误的输出的输出端的比较器电路 绑在未调节的电压（VCHP）和细胞（REFC）的阈值电压，和调节器电路之间的差信号（ID）（CSEL，CBIAS，IVC，DRV，TR）耦合到所述比较器电路的输出端和 可操作以调节基于电动误差信号（ID）的值的未稳压电压（VCHP）。 通过本电路中，经调节的电压（RV）是由可编程的，并且依赖于存储单元（REFC）的参数。

    An electrically modifiable, non-volatile, semiconductor memory which can keep a datum stored until an operation to modify the datum is completed
    8.
    发明公开
    An electrically modifiable, non-volatile, semiconductor memory which can keep a datum stored until an operation to modify the datum is completed 有权
    保持写入数据的电可修改非易失性半导体存储器，直到它们的重新编程完成

    公开(公告)号：EP1220229A1

    公开(公告)日：2002-07-03

    申请号：EP00830878.5

    申请日：2000-12-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Gastaldi, Roberto ,  Lo Giudice, Gianbattista ,  Pasotti, Marco ,  Pio, Federico

    IPC: G11C16/10

    CPC classification number: G11C16/102

    Abstract: An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify user memory location, there is a corresponding pair of physical memory locations ((X1, Y1), (X2, Y2); WORDn) in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.

    Abstract translation: 的电可修改，非易失性半导体存储器包括可以单独地被寻址的存储器外，以便读取和修改用户的存储位置的用户存储器位置的复数，有一对相应的物理存储器位置（（X1 ，Y1），（X2，Y2）;在所述存储器中，其中假设，WORDn）可选地，有源存储器位置和一个非活性的存储器位置的功能，活性存储器位置包含先前写入的日期和非 -active存储单元是可用于新的日期的书面替换先前写的日期，使得在更换以前的日期与新日期的请求，先前的日期是保存在内存，直到新的日期有 被写入。

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