公开(公告)号：EP4529382A1

公开(公告)日：2025-03-26

申请号：EP24199611.5

申请日：2024-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Hongjun ,  LEE, Kiseok ,  KIM, Huijung ,  SONG, Younggeun ,  LEE, Yongjin

IPC: H10B12/00 ,  H10D30/67

Abstract: A semiconductor device includes bit lines, channels, a first capping pattern, a gate insulation pattern, a gate electrode and capacitors. The bit lines are on a substrate, and each of the bit lines extends in a first direction. The bit lines are spaced apart from each other in a second direction. The channels are spaced apart from each other in the first direction. The first capping pattern is on a sidewall of each of the channels. The gate insulation pattern is on a sidewall of the first capping pattern. The gate electrode is on a sidewall of the gate insulation pattern. The capacitors are electrically connected to respective ones of the channels.

公开(公告)号：EP4496448A1

公开(公告)日：2025-01-22

申请号：EP24166002.6

申请日：2024-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： KANG, Minju ,  KIM, Jongmin ,  PARK, SangJae ,  PARK, Sohyun ,  LEE, Kiseok

IPC: H10B12/00

Abstract: A semiconductor device includes a first active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction, a first word line between the first edge portion and the second edge portion and extending in a second direction intersecting the first direction, a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction, and a storage node contact on the second edge portion, where the first edge portion includes a first top surface and a second top surface, and the second top surface of the first edge portion is closer to the second edge portion than the first top surface of the first edge portion.

公开(公告)号：EP4489543A2

公开(公告)日：2025-01-08

申请号：EP24179083.1

申请日：2024-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Bongsoo ,  KIM, Yongkwan ,  KIM, Jongmin ,  PARK, Taejin ,  YOON, Chansic ,  HAN, Jinwoo

IPC: H10B12/00

Abstract: A semiconductor device includes an active array in which a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction and crossing central portions of the active patterns; a bit line structure contacting first portions of the active patterns adjacent to a first sidewall of the gate structure and extending in a second direction; and a capacitor electrically connected to a second portion of each of the active patterns adjacent to a second sidewall of the gate structure. In a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction oblique with respect to the first direction. The active patterns arranged side by side in the second direction form an active column.

公开(公告)号：EP4429432A1

公开(公告)日：2024-09-11

申请号：EP23213538.4

申请日：2023-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： KIM, Jongmin ,  LEE, Kiseok ,  KO, Seung-Bo ,  YOON, Chan-sic ,  LEE, Myeong-Dong

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/485

Abstract: A semiconductor device including a first active pattern and a second active pattern each extending along a first direction and arranged along a second direction intersecting the first direction each of the first and second active patterns including a central part, a first edge part, and a second edge part, a storage node pad on the first edge part of the first active pattern, and a bit-line node contact on the central part of the first active pattern, wherein a top surface of the bit-line node contact is located at a higher level than a top surface of the storage node pad may be provided.

公开(公告)号：EP4284138A1

公开(公告)日：2023-11-29

申请号：EP23155116.9

申请日：2023-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： PARK, Seokhan ,  LEE, Kiseok ,  SHIN, Seokho ,  CHOI, Hyungeun ,  YOO, Bowon

IPC: H10B12/00 ,  H01L21/764 ,  H01L29/786

Abstract: A semiconductor device includes bit line structures (360, 350, 340) on a substrate. Each bit line structure extends in a second direction, and the bit line structures are spaced apart from each other in a first direction. The semiconductor device further includes semiconductor patterns (137) spaced apart from each other in the second direction on each of the bit line structures, insulating interlayer patterns between neighboring ones of the semiconductor patterns in the first direction, and word lines (305) spaced apart from each other in the second direction on the bit line structures. Each word line extends in the first direction adjacent to the semiconductor patterns. The semiconductor device further includes capacitors (700) disposed on and electrically connected to the semiconductor patterns, respectively. A seam (181) extending in the second direction is formed in each of the insulating interlayer patterns (185).

公开(公告)号：EP4274401A1

公开(公告)日：2023-11-08

申请号：EP23163434.6

申请日：2023-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  JEONG, Moonyoung ,  KIM, Keunnam ,  PARK, Seokhan

IPC: H10B12/00 ,  H01L29/786

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device includes a bit line (BL; 161, 163) extending in a first direction, first and second active patterns (AP1, AP2) disposed on the bit line (BL), a back-gate electrode (BG), which is disposed between the first and second active patterns (AP1, AP2) and is extended in a second direction to cross the bit line (BL), a first word line (WL1), which is provided at a side of the first active pattern (AP1) and is extended in the second direction, a second word line (WL2), which is provided at an opposite side of the second active pattern (AP2) and is extended in the second direction, and contact patterns (BC) coupled to the first and second active patterns (AP1, AP2), respectively.

公开(公告)号：EP4195899A1

公开(公告)日：2023-06-14

申请号：EP22204514.8

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  CHOI, Hyungeun ,  KANG, Gijae ,  KIM, Keunnam ,  YIM, Soobin ,  JEONG, Moonyoung ,  JUNG, Seungjae

IPC: H10B12/00

Abstract: Semiconductor memory devices may include a cell array structure that may include a memory cell array including three-dimensionally arranged memory cells and first bonding pads connected to the memory cell array and a peripheral circuit structure that may include peripheral circuits and second bonding pads bonded to the first bonding pads. The cell array structure may include a lower dielectric layer having a first surface and a second surface opposite to the first surface, a stack structure including horizontal electrodes stacked in a vertical direction on the first surface of the lower dielectric layer, a vertical structure including vertical conductive patterns that extend in the vertical direction and cross the horizontal electrodes, and an input/output pad on the second surface of the lower dielectric layer.

公开(公告)号：EP4138133A1

公开(公告)日：2023-02-22

申请号：EP22166736.3

申请日：2022-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Keunnam ,  KIM, Hui-Jung ,  LEE, Wonsok ,  CHO, Min Hee

IPC: H01L27/108

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

公开(公告)号：EP4092742A1

公开(公告)日：2022-11-23

申请号：EP22156841.3

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Hui-Jung ,  CHO, Min Hee

IPC: H01L27/108

Abstract: A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

公开(公告)号：EP3975258A1

公开(公告)日：2022-03-30

申请号：EP21180703.7

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  LEE, Kyunghwan ,  KIM, Dongoh ,  KIM, Yongseok ,  KIM, Hui-Jung ,  CHO, Min Hee

IPC: H01L27/24 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor memory device includes a bit line (BL) extending in a first direction (Dl), a channel pattern (CP) on the bit line, the channel pattern including first and second vertical portions (VP1, VP2) facing each other and a horizontal portion (HP) connecting the first and second vertical portions, first and second word lines (WL1, WL2) provided on the horizontal portion and between the first and second vertical portions and extended in a second direction (D2) crossing the bit line, and a gate insulating pattern (Gox) provided between the first word line and the channel pattern and between the second word line and the channel pattern.