公开(公告)号：EP4415497A3

公开(公告)日：2024-08-28

申请号：EP23205348.8

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Wonsok ,  LEE, Juho ,  KIM, Seunghyun ,  JUNG, Wooje ,  CHO, Minhee

IPC: H10B12/00 ,  H01L29/786

CPC classification number: H10B12/05 ,  H01L29/7869 ,  H10B12/0335 ,  H10B12/315 ,  H01L29/78642

Abstract: A semiconductor memory device, which may include a substrate, a lower conductive line on the substrate, an isolation insulating layer on the lower conductive line and including a channel trench, a channel structure inside the channel trench and including a first oxide semiconductor material, an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure, a gate dielectric layer that covers the channel structure within the channel trench, an upper conductive line on the gate dielectric layer within the channel trench, a conductive contact pattern on the channel structure, an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and including a second oxide semiconductor material, and a capacitor structure including a lower electrode connected to the conductive contact pattern.

公开(公告)号：EP4138133A1

公开(公告)日：2023-02-22

申请号：EP22166736.3

申请日：2022-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Keunnam ,  KIM, Hui-Jung ,  LEE, Wonsok ,  CHO, Min Hee

IPC: H01L27/108

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

公开(公告)号：EP4415497A2

公开(公告)日：2024-08-14

申请号：EP23205348.8

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Wonsok ,  LEE, Juho ,  KIM, Seunghyun ,  JUNG, Wooje ,  CHO, Minhee

IPC: H10B12/00 ,  H01L29/786

CPC classification number: H10B12/05 ,  H01L29/7869 ,  H10B12/0335 ,  H10B12/315 ,  H01L29/78642

Abstract: A semiconductor memory device, which may include a substrate, a lower conductive line on the substrate, an isolation insulating layer on the lower conductive line and including a channel trench, a channel structure inside the channel trench and including a first oxide semiconductor material, an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure, a gate dielectric layer that covers the channel structure within the channel trench, an upper conductive line on the gate dielectric layer within the channel trench, a conductive contact pattern on the channel structure, an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and including a second oxide semiconductor material, and a capacitor structure including a lower electrode connected to the conductive contact pattern.

公开(公告)号：EP4274400A1

公开(公告)日：2023-11-08

申请号：EP23156274.5

申请日：2023-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KU, Byeongjoo ,  KIM, Keunnam ,  LEE, Wonsok ,  JEONG, Moonyoung ,  CHO, Min Hee

IPC: H10B12/00 ,  H01L29/786

Abstract: A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, first and second word lines adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the first and second vertical portions is located at a height that is lower than or equal to the uppermost surface of the bit line.

公开(公告)号：EP4254512A1

公开(公告)日：2023-10-04

申请号：EP22217287.6

申请日：2022-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOO, Sungwon ,  KIM, Yongseok ,  RYU, Min, Tae ,  RYU, Huije ,  LEE, Yongjin ,  LEE, Wonsok ,  CHO, Min, Hee

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern include oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.

公开(公告)号：EP4138134A1

公开(公告)日：2023-02-22

申请号：EP22167093.8

申请日：2022-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Keunnam ,  KIM, Hui-Jung ,  LEE, Wonsok ,  CHO, Min Hee

IPC: H01L27/108

Abstract: A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.