公开(公告)号：FR2772985B1

公开(公告)日：2000-05-26

申请号：FR9804236

申请日：1998-04-06

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH WEI

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L29/78 ,  H01L23/52

公开(公告)号：FR2774809A1

公开(公告)日：1999-08-13

申请号：FR9812017

申请日：1998-09-25

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI RUNG ,  LUR WATER ,  SUN SHIH WEI ,  HUANG YIMIN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78 ,  H01L23/528

Abstract: A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

公开(公告)号：FR2763743A1

公开(公告)日：1998-11-27

申请号：FR9711068

申请日：1997-09-05

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.

公开(公告)号：FR2755793A1

公开(公告)日：1998-05-15

申请号：FR9613737

申请日：1996-11-12

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH WEI

IPC: H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: A silicon on insulator (SOI) memory comprises: (a) a substrate (10) having a silicon surface layer covering a buried silicon oxide layer (12); (b) field isolation regions (14) on the substrate surface, extending through the silicon layer and in contact with the buries silicon oxide layer, to define active device regions on the silicon surface layer; (c) first and second source/drain regions (24), formed in the active device regions to define channel regions in the silicon surface layer; (d) a gate oxide layer on the channel region, with a gate electrode (18) on top; (e) a trench formed through the first source/drain region and the silicon surface layer, and into the buried silicon oxide layer; and (f) a lower capacitor electrode (32) extending into the trench, with a dielectric layer (34) and an upper capacitor electrode (36) formed on top. Also claimed is a method of making the above SOI memory.