公开(公告)号：GB2328078A

公开(公告)日：1999-02-10

申请号：GB9716395

申请日：1997-08-01

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/08

Abstract: A method of making a MOS device comprising a self-aligned silicide layer 31 and an impurity diffusion region 29 in a lower part of the source/drain regions 23a adjacent to an isolating region 24, includes over-etching (Figure 2B) the isolating regions 24 to expose the surface of the source/drain regions. Ion implantation (Figure 2C) at a large tilt angle increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window 34, resulting in a lowering of both contact resistance and sheet resistance.

公开(公告)号：DE19734837A1

公开(公告)日：1998-11-26

申请号：DE19734837

申请日：1997-08-12

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

Abstract: The method involves, on a substrate (21), depositing a first insulation layer (25), which is anisotropically over-etched to remove the layer and to form spacing elements (26) on corresponding side walls of the gate region (23) and for simultaneous removing a part of the top layer of the insulator regions (24). Second type ions are implanted with an inclination angle into the metal-oxide-semiconductor (MOS) component region (22), using the spacing elements and gate region as a mask to form several source/drain regions (27) in the substrate on each side of the gate region. A metal film is formed on a substrate surface, the MOS component region and the spacing elements. A rapid thermal treatment results in a metal-silicide layer (31), followed by specified process steps.

公开(公告)号：FR2758210A1

公开(公告)日：1998-07-10

申请号：FR9700024

申请日：1997-01-03

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LUR WATER ,  LIN TONY

IPC: H04B10/10 ,  H01L29/49 ,  H01L21/28

Abstract: The infrared transmitter includes a transmission device with transmitter and receiver on a computer. A second transmission device includes a transmitter and receiver on a keyboard. A transmission angle adjustment mask is arranged on the first or second transmission device to adjust the transmission angle of the device. A spherical direction adjustment device is included.

公开(公告)号：FR2758210B1

公开(公告)日：1999-03-26

申请号：FR9700024

申请日：1997-01-03

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LUR WATER ,  LIN TONY

IPC: H04B10/10 ,  H01L29/49 ,  H01L21/28

公开(公告)号：GB2320134A

公开(公告)日：1998-06-10

申请号：GB9625264

申请日：1996-12-04

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LUR WATER ,  LIN TONY

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/283

Abstract: Salicide (self-aligned silicide) electrodes are formed using a process that does not require oxide spacer structures alongside polysilicon gate electrodes and wiring lines. A shaped polysilicon electrode 58 is formed having protrusions. LDD source/drain regions 66 are formed in semiconductor substrate 10 by ion implantation using the polysilicon gate electrode as a mask. Physical vapor deposition is used to deposit a metal layer 70, e.g. of titanium, having discontinuities under the protrusions. A first rapid thermal anneal is performed to cause the metal to form a metal silicide over the polysilicon electrode 58. Unreacted metal is etched and then a second rapid thermal anneal is performed to convert the metal silicide to its lowest resistivity phase, the metal silicide extending laterally beyond the edges of the electrode protrusions. Gate electrodes 58 and wiring lines 60 having this structure generally are formed having lower stress in the silicide layers, producing salicide structures having lower resistance than gate electrodes and wiring lines formed using conventional salicide techniques.

公开(公告)号：GB2360128A

公开(公告)日：2001-09-12

申请号：GB0113671

申请日：1996-12-04

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LUR WATER ,  LIN TONY

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/283

Abstract: Salicide (self-aligned silicide) electrodes are formed using a process that does not require oxide spacer structures alongside polysilicon gate electrodes and wiring lines. The process comprises forming insulating layer (56) over semiconductor substrate (10), forming a shaped polysilicon structure (58) with laterally extending protrusions (62) over insulating layer (56), and depositing metal layer (70) (e.g. titanium) over the polysilicon structure (58), preferably by physical vapour deposition, and annealing the metal layer (70), preferably by rapid thermal annealing at about 700{ for 10 to 120 seconds to produce metal silicide layer (74, Fig. 15). The polysilicon structure (58) can be the electrode of a MOS transistor, where lightly-doped source and drain regions (64) are formed by ion implantation with the protrusions (62) acting as a mask for the implantation. Gate electrodes (58) and wiring lines (60) fabricated by this method have lower stress in the silicide layers, producing salicide structures having lower resistance than gate electrodes and wiring lines formed using conventional salicide techniques.

公开(公告)号：GB2328078B

公开(公告)日：1999-07-14

申请号：GB9716395

申请日：1997-08-01

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/08

Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.

公开(公告)号：FR2763743A1

公开(公告)日：1998-11-27

申请号：FR9711068

申请日：1997-09-05

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.

公开(公告)号：DE19734837B4

公开(公告)日：2004-04-15

申请号：DE19734837

申请日：1997-08-12

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.

公开(公告)号：FR2763743B1

公开(公告)日：1999-07-23

申请号：FR9711068

申请日：1997-09-05

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.