公开(公告)号：WO2017146798A1

公开(公告)日：2017-08-31

申请号：PCT/US2016/065189

申请日：2016-12-06

Applicant: XILINX, INC.

Inventor： TURKER MELEK, Didem Z. ,  UPADHYAYA, Parag ,  CHANG, Kun-Yung

IPC: H03G1/00 ,  H03G3/30 ,  H04L25/03

CPC classification number: H03G3/3036 ,  H03F1/0205 ,  H03F1/0211 ,  H03F3/16 ,  H03F3/45197 ,  H03F2200/555 ,  H03F2203/45492 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/301 ,  H04B1/123 ,  H04L25/03885

Abstract: An example automatic gain control (AGC) circuit (206) includes a base current-gain circuit (302) having a programmable source degeneration resistance (304) responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit (308), coupled between an input (328) and an output (330) of the base current-gain circuit, having a programmable current source (312) responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit (314), coupled to the output of the base current-gain circuit, having a programmable current source (316) responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit (318) coupled to the output of the base current-gain circuit.

Abstract translation: 示例性自动增益控制（AGC）电路（206）包括具有响应于AGC码字的第一位的可编程源极负反馈电阻（304）的基极电流增益电路（302）。 AGC电路进一步包括可编程电流增益电路（308），耦合在基本电流增益电路的输入（328）和输出（330）之间，具有响应于基极电流增益电路的第二位 AGC码字。 AGC电路还包括耦合到基极电流增益电路的输出端的泄放电路（314），其具有响应于AGC码字的第二位的逻辑补码的可编程电流源（316）。 AGC电路还包括耦合到基极电流增益电路的输出的负载电路（318）。

公开(公告)号：WO2015030877A1

公开(公告)日：2015-03-05

申请号：PCT/US2014/033527

申请日：2014-04-09

Applicant: XILINX, INC.

Inventor： SEWANI, Aman ,  UPADHYAYA, Parag

IPC: H03K19/177

CPC classification number: H03K19/018521 ,  H03K19/17744 ,  H03K19/1778 ,  H03K19/17788

Abstract: An input/output circuit (102) implemented in an integrated circuit (100) is described. The input/output circuit comprises an input/output pad (202, 204) and a voltage control circuit (229) coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad (RX Mode control: high) and at a second voltage when the input/output pad is implemented as an output pad (RX Mode Control: low). Methods of implementing input/output circuits in an integrated circuit are also described.

Abstract translation: 描述了在集成电路（100）中实现的输入/输出电路（102）。 输入/输出电路包括耦合到输入/输出焊盘的输入/输出焊盘（202,204）和电压控制电路（229）。 当输入/输出焊盘实现为输入焊盘（RX模式控制：高）时，电压控制电路以第一电压设置输入/输出焊盘处的电压，并且当输入/输出焊盘实现为 输出板（RX模式控制：低）。 还描述了在集成电路中实现输入/输出电路的方法。

公开(公告)号：WO2014065905A1

公开(公告)日：2014-05-01

申请号：PCT/US2013/049319

申请日：2013-07-03

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  UPADHYAYA, Parag

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01F17/00

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor structure implemented within a semiconductor integrated circuit (IC) includes a coil (105) of conductive material including at least one turn and a current return (130, 500) encompassing the coil. The current return is formed of a plurality of interconnected metal layers (510, 515, 520, 525) of the semiconductor integrated circuit.

Abstract translation: 在半导体集成电路（IC）内实现的电感器结构包括包括至少一个匝的导电材料的线圈（105）和包围线圈的电流返回（130,500）。 电流返回由半导体集成电路的多个互连金属层（510,515,520,525）形成。

公开(公告)号：WO2013106088A1

公开(公告)日：2013-07-18

申请号：PCT/US2012/050858

申请日：2012-08-15

Applicant: XILINX, INC. ,  UPADHYAYA, Parag

Inventor： UPADHYAYA, Parag

IPC: H03B1/00

CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1293

Abstract: A resonator circuit enabling temperature compensation includes an inductor (104) coupled between a first node (108) and a second node (1 10) of the resonator circuit; a capacitor circuit (106) coupled between the first node and the second node; and a temperature compensation circuit (1 12) coupled between the first node and the second node. The temperature compensation circuit comprises a varactor (302) coupled to receive a temperature control signal (304) that sets the capacitance of the varactor. A method of generating a resonating output is also disclosed.

Abstract translation: 实现温度补偿的谐振器电路包括耦合在谐振器电路的第一节点（108）和第二节点（110）之间的电感器（104） 耦合在所述第一节点和所述第二节点之间的电容器电路（106） 以及耦合在第一节点和第二节点之间的温度补偿电路（112）。 温度补偿电路包括耦合以接收设置变容二极管的电容的温度控制信号（304）的变容二极管（302）。 还公开了一种产生谐振输出的方法。

公开(公告)号：WO2012128832A1

公开(公告)日：2012-09-27

申请号：PCT/US2012/021079

申请日：2012-01-12

Applicant: XILINX, INC. ,  WU, Zhaoyin, D. ,  JIANG, Xuewen ,  UPADHYAYA, Parag ,  JING, Jing ,  WU, Shuxian

Inventor： WU, Zhaoyin, D. ,  JIANG, Xuewen ,  UPADHYAYA, Parag ,  JING, Jing ,  WU, Shuxian

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor structure (105, 500, 900) implemented within a semiconductor integrated circuit (IC) can include a coil (205, 505, 905) of conductive material that includes a center terminal (140, 510, 910) located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline (225, 535, 935) bisecting the center terminal. The coil can include a first differential terminal (210, 515, 915) and a second differential terminal (215, 520, 920). The inductor structure can include a return line (155, 560, 960) of conductive material positioned on the center line. The inductor structure can include an isolation ring (220, 525, 945) surrounding the coil. The inductor structure can include a patterned ground shield comprising a plurality of fingers (935, 1035) implemented within an IC process layer located between the coil (905) and a substrate (955) of the IC. The inductor structure can include an isolation wall (1 150) comprising a high conductive material formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger of the patterned ground shield.

Abstract translation: 实现在半导体集成电路（IC）内的电感器结构（105,500,900）可以包括导电材料的线圈（205,505,905），其包括位于中间端子（140,510,910）的中点 线圈的长度。 线圈可相对于将中心线平分的中心线（225,535,935）对称。 线圈可以包括第一差分端子（210,515,915）和第二差分端子（215,520,920）。 电感器结构可以包括位于中心线上的导电材料的返回线（155,560,960）。 电感器结构可以包括围绕线圈的隔离环（220,525,945）。 电感器结构可以包括图案化的接地屏蔽，其包括在位于线圈（905）和IC的衬底（955）之间的IC处理层内实现的多个指状物（935,1035）。 电感器结构可以包括隔离壁（115），其包括形成为包围线圈和图案化接地屏蔽的高导电材料。 隔离壁可以连接到图案化的接地屏蔽的每个手指的一端。

公开(公告)号：EP4449613A1

公开(公告)日：2024-10-23

申请号：EP22789368.2

申请日：2022-09-14

Applicant: Xilinx, Inc.

Inventor： MA, Shaojun ,  POON, Chi Fung ,  ZHENG, Kevin ,  UPADHYAYA, Parag

IPC: H03L7/099 ,  H03L7/24

公开(公告)号：EP4218137A1

公开(公告)日：2023-08-02

申请号：EP21746897.4

申请日：2021-07-07

Applicant: Xilinx, Inc.

Inventor： RAJ, Mayank ,  UPADHYAYA, Parag

IPC: H03K19/0185 ,  H04B10/516 ,  H04B17/18

公开(公告)号：EP3566247A1

公开(公告)日：2019-11-13

申请号：EP17830033.1

申请日：2017-11-30

Applicant: Xilinx, Inc.

Inventor： UPADHYAYA, Parag ,  JING, Jing

IPC: H01L23/522

公开(公告)号：EP3440774A1

公开(公告)日：2019-02-13

申请号：EP17718759.8

申请日：2017-04-06

Applicant: Xilinx, Inc.

Inventor： NANDWANA, Romesh K. ,  UPADHYAYA, Parag

IPC: H03L7/08 ,  H03L7/099

CPC classification number: H03L7/24 ,  H03L7/0805 ,  H03L7/081 ,  H03L2207/06 ,  H03L2207/50

Abstract: An example clock generator circuit includes a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) that delays the reference clock based on a first control code, and a pulse generator configured to generate pulses based on the delayed reference clock. The clock generator circuit includes a digitally controlled oscillator (DCO) configured to generate an output clock based on a second control code, the DCO including an injection input coupled to the pulse generator to receive the pulses. The clock generator circuit includes a phase detector configured to compare the output clock and the reference clock and generate the phase error signal, and a control circuit configured to generate the first and second control codes based on the phase error signal.

公开(公告)号：EP3281294A1

公开(公告)日：2018-02-14

申请号：EP15816596.9

申请日：2015-12-01

Applicant: Xilinx, Inc.

Inventor： ZHANG, Wenfeng ,  UPADHYAYA, Parag

IPC: H03K19/0185 ,  H03K19/094

CPC classification number: H03K19/018514 ,  H03K19/09432

Abstract: A common mode logic buffer device includes a current source configured to provide a source current. An input stage includes a first MOS transistor pair configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair.