公开(公告)号：WO2023043509A1

公开(公告)日：2023-03-23

申请号：PCT/US2022/032029

申请日：2022-06-02

Applicant: XILINX, INC.

Inventor： CASEY, Ronan Sean ,  RAJENDRAN, Lokesh ,  CAREY, Declan ,  ZHENG, Kevin ,  HEARNE, Catherine ,  ZHANG, Hongtao

IPC: H04L25/02 ,  G06F13/00 ,  H04L25/49 ,  H04L27/04

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

公开(公告)号：WO2021183202A1

公开(公告)日：2021-09-16

申请号：PCT/US2020/067191

申请日：2020-12-28

Applicant: XILINX, INC.

Inventor： CHO, Junho ,  ZHENG, Kevin ,  UPADHYAYA, Parag

IPC: H03K19/017 ,  H03F1/42

Abstract: Electronic devices that include a continuous time linear equalizer, CTLE, are provided. An example of a CTLE includes a first inverter (402); a second inverter (404) having an input to receive an input signal (IN); a capacitor (408) coupled between an input of the first inverter (402) and the input of the second inverter (404); a resistor (410) coupled between a common-mode voltage (VCM) and the input of the first inverter; a third inverter (406) having an output to provide an output signal (Out); and a node (416) comprising an output of the first inverter (404), an output of the second inverter (402), an input of the third inverter (406), and the output of the third inverter.

公开(公告)号：EP4449613A1

公开(公告)日：2024-10-23

申请号：EP22789368.2

申请日：2022-09-14

Applicant: Xilinx, Inc.

Inventor： MA, Shaojun ,  POON, Chi Fung ,  ZHENG, Kevin ,  UPADHYAYA, Parag

IPC: H03L7/099 ,  H03L7/24

公开(公告)号：EP4118747A1

公开(公告)日：2023-01-18

申请号：EP20845512.1

申请日：2020-12-28

Applicant: Xilinx, Inc.

Inventor： CHO, Junho ,  ZHENG, Kevin ,  UPADHYAYA, Parag

IPC: H03K19/017 ,  H03F1/42

公开(公告)号：EP4402867A1

公开(公告)日：2024-07-24

申请号：EP22740591.7

申请日：2022-06-02

Applicant: Xilinx, Inc.

Inventor： CASEY, Ronan Sean ,  RAJENDRAN, Lokesh ,  CAREY, Declan ,  ZHENG, Kevin ,  HEARNE, Catherine ,  ZHANG, Hongtao

IPC: H04L25/02 ,  G06F13/00 ,  H04L25/49 ,  H04L27/04

CPC classification number: H04L25/4917 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0266