公开(公告)号：JP2591286B2

公开(公告)日：1997-03-19

申请号：JP22917990

申请日：1990-08-30

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/02 ,  H03M3/04

公开(公告)号：JPH04179316A

公开(公告)日：1992-06-26

申请号：JP30790190

申请日：1990-11-14

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04

Abstract: PURPOSE:To reduce loopback noise and to improve an S/N by cancelling a noninverted digital input and an inverted digital input coming suddenly to a clock generation means, and preventing the mixing of data noise with a system clock signal. CONSTITUTION:A second input signal line 24 is arranged in parallel to a first input signal line 20 guiding a digital input to a noise shaper 12 and an inversion means 22 inverting the digital input and transmitting it is provided. The inverted digital input from the inversion means 22 is supplied to the second input signal line 22. The noninverted digital input from the first input signal line 20 and the inverted digital input from the second input signal line 24 coming suddenly to the clock oscillation terminal of the clock generator. Since the phases of the inputs are opposite and sizes are almost equal, they cancel each other and power as noise comes to considerably small. Thus, the loopback nose is reduced and the S/N can be improved.

公开(公告)号：JPH04129427A

公开(公告)日：1992-04-30

申请号：JP25117390

申请日：1990-09-20

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04

Abstract: PURPOSE:To reduce reflected noise based on a data noise mixed in a system clock by deciding a transmission frequency of a digital input so as to be equal to an integral number of multiple of the system clock number of a noise shaper or its vicinity. CONSTITUTION:A transmission frequency fs to a noise shaper 12 is decided to be equal to a multiple of (n) of the frequency fs of a system clock signal phis or its vicinity, where (n) is a positive integer. Thus, let (n) be 1, mixed noise in the system clock is caused at the frequency fs in which noise power is minimum and in the vicinity. Thus, reflected noise is minimized.

公开(公告)号：JPH04115717A

公开(公告)日：1992-04-16

申请号：JP23519290

申请日：1990-09-05

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  KISHII TATSUYA ,  MORITA KUNIAKI ,  HOSHI JURO

IPC: H03K17/687 ,  H03K19/0948

Abstract: PURPOSE:To prevent an oscillation from being caused in the switching output by connecting plural transistors(TRs) of a same conduction form in series and connecting an output terminal to TRs at one end of the series connection path. CONSTITUTION:When an input X rises to 1, N-channel MOS TRs T1, T10 are both turned on and a P-channel MOS TR T2 is turned off, an output, the inverse of X goes to 0. Then a TR T3 is turned off in response to a change of the output, the inverse of X to 0 and then a TR T4 is turned on, then an output Y goes to 1. When the input X falls down to 0, both the TRs T1, T10 are turned off and the TR T2 is turned on, then the output, the inverse of X goes to 1. In this case, since a path of a displacement current via a back gate-drain junction capacitance of the TR T1 is interrupted by the turning-off of the TR T10, no oscillation takes place at the output, the inverse of X. Since the TR T3 is turned on and the TR T4 is turned off in response to a change of the output, the inverse of X to logical 1, the output Y goes to 0. In this case, since no oscillation takes place at the output, the inverse of X, no oscillation is caused at the output Y.

公开(公告)号：JP2011066559A

公开(公告)日：2011-03-31

申请号：JP2009213808

申请日：2009-09-15

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KISHII TATSUYA ,  MAEJIMA TOSHIO ,  TSUCHIYA HIROTOSHI ,  NAKAMURA KATSUYOSHI ,  MIYAZAKI MASAHITO ,  HIMENO AKIHISA

IPC: H03F3/217 ,  H03G11/00

Abstract: PROBLEM TO BE SOLVED: To provide a class-D amplifier capable of performing dynamic range compression with a simple configuration without requiring an external circuit such as a variable resistor. SOLUTION: An error integrator 110 integrates an error between an input signal and a feedback signal and outputs an integral value signal indicating an integral value. A pulse-width modulating circuit 130 outputs a digital signal having pulse width corresponding to the level of the integral value signal. An output buffer 150 drives a load based upon a digital signal output from the pulse-width modulating circuit 130. An output signal of the output buffer 150 is fed back to the error integrator 110. A compression characteristic control section 330 generates a compression characteristic control signal generated by multiplying a peak of Vin by a gain corresponding to a specified compression ratio, and adding a specified threshold. An attenuation instruction generating section 380 outputs an attenuation instruction pulse SW once the level of the output signal of the output buffer 150 exceeds the level of the compression characteristic control signal. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供能够以简单的配置执行动态范围压缩的D类放大器，而不需要诸如可变电阻器的外部电路。 解决方案：误差积分器110对输入信号和反馈信号之间的误差进行积分，并输出表示积分值的积分值信号。 脉冲宽度调制电路130输出具有与积分值信号的电平对应的脉冲宽度的数字信号。 输出缓冲器150基于从脉冲宽度调制电路130输出的数字信号来驱动负载。输出缓冲器150的输出信号被反馈到误差积分器110.压缩特性控制部分330产生压缩特性控制 通过将Vin的峰值乘以与指定压缩比相对应的增益而生成的信号，并且添加指定的阈值。 一旦输出缓冲器150的输出信号的电平超过压缩特性控制信号的电平，衰减指令产生部件380输出衰减指令脉冲SW。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009094568A

公开(公告)日：2009-04-30

申请号：JP2007260263

申请日：2007-10-03

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TSUCHIYA HIROTOSHI ,  YAEZAWA SHINJI ,  HASHIMOTO YUYA ,  NAKAMORI TORU ,  KISHII TATSUYA

IPC: H03K4/06

Abstract: PROBLEM TO BE SOLVED: To generate triangular waves of which a wave-height value is adjusted to a desired value. SOLUTION: A triangular wave generation circuit comprises: a comparator CMP1 for comparing a triangular wave signal TRI taken out of the terminal of a capacitor C with a reference voltage TRIPH; and a current value adjustment circuit 3 for decreasing or increasing a current value for charging or discharging the capacitor C monotonously by turning on or off respective constant current sources IS11-IS15, IS21-IS25 of first and second constant current source groups IS1, IS2, and holding the on/off state of each constant current source at that point in time when detecting that the changing wave-height value of the triangular wave signal TRI at that time goes lower or higher than that determined by the reference voltage TRIPH based on output CMP_OUT of the comparator CMP1. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：产生波高值被调整到期望值的三角波。 解决方案：三角波产生电路包括：比较器CMP1，用于将从电容器C的端子取出的三角波信号TRI与参考电压TRIPH进行比较; 以及电流值调节电路3，用于通过接通或断开第一和第二恒定电流源组IS1，IS2的各个恒定电流源IS11-IS15，IS21-IS25来逐渐减小或增大用于对电容器C进行充电或放电的电流值， 并且当检测到该时刻的三角波信号TRI的变化波高值基于输出而变为低于或高于基准电压TRIPH所确定的时间点时，保持每个恒定电流源的开/关状态 比较器CMP1的CMP_OUT。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009089195A

公开(公告)日：2009-04-23

申请号：JP2007258159

申请日：2007-10-01

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TSUCHIYA HIROTOSHI ,  YAEZAWA SHINJI ,  HASHIMOTO YUYA ,  NAKAMORI TORU ,  KISHII TATSUYA

IPC: H03F3/45 ,  H03F1/00

CPC classification number: H03F3/45183 ,  H03F1/52 ,  H03F2203/45352 ,  H03F2203/45594 ,  H03F2203/45674

Abstract: PROBLEM TO BE SOLVED: To provide a differential amplifier prevented from entering an abnormal operating state, where differential amplification is not performed, even when an input signal exceeding an in-phase input range is applied. SOLUTION: In a differential amplifier 100, input signals IP and IN are applied to gates of field effect transistors 111 and 112 constituting a differential transistor pair. Based on drain voltages of the P-channel field effect transistors 111 and 112, output signals OP and ON are then generated as a differential amplification result. When starting the differential amplifier 100, an initialization control unit 170 turns on P-channel field effect transistors 171 and 162 over a predetermined time to form first and second current paths in parallel with the P-channel field effect transistors 111 and 112. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：即使当施加超过同相输入范围的输入信号时，提供一种防止不进行差分放大的异常工作状态的差分放大器。 解决方案：在差分放大器100中，将输入信号IP和IN施加到构成差分晶体管对的场效应晶体管111和112的栅极。 基于P沟道场效应晶体管111和112的漏极电压，然后产生输出信号OP和ON作为差分放大结果。 当启动差分放大器100时，初始化控制单元170在预定时间内导通P沟道场效应晶体管171和162，以形成与P沟道场效应晶体管111和112并联的第一和第二电流路径。

版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009089192A

公开(公告)日：2009-04-23

申请号：JP2007258132

申请日：2007-10-01

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TSUCHIYA HIROTOSHI ,  YAEZAWA SHINJI ,  HASHIMOTO YUYA ,  NAKAMORI TORU ,  KISHII TATSUYA

IPC: H03K17/00 ,  H01L21/822 ,  H01L27/04 ,  H03K19/007

Abstract: PROBLEM TO BE SOLVED: To stably shift each semiconductor integrated circuit into a power-down state when wired-ORing of error detecting signals outputted from a plurality of semiconductor integrated circuits and applying a result thereof to the semiconductor integrated circuits as a power-down command signal. SOLUTION: In the semiconductor integrated circuit, a delay circuit 15 is interposed between a power-down control circuit 14 and an error detection circuit 11. The power-down control circuit 14 turns a power-down control signal to an active level when a power-down command signal PDN from the outside is less than a threshold of an inverter 13, and the error detection circuit 11 turns an error detecting signal ERN to an active level by turning on an N-channel field effect transistor 12 in response to detection of an error when the power-down control signal is at an inactive level. Even after the power-down command signal PDN is less than the threshold of the inverter 13, the error detecting signal ERN is continuously changed from inactive level to active level. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了在从多个半导体集成电路输出的误差检测信号进行布线或将其结果作为功率施加到半导体集成电路时将每个半导体集成电路稳定地移位到掉电状态 -down命令信号。 解决方案：在半导体集成电路中，在断电控制电路14和误差检测电路11之间插入延迟电路15.断电控制电路14将掉电控制信号转换到有效电平 当来自外部的断电命令信号PDN小于反相器13的阈值时，并且误差检测电路11通过接通N沟道场效应晶体管12来响应于误差检测信号ERN而变为有效电平 以在断电控制信号处于非活动电平时检测错误。 即使在断电命令信号PDN小于反相器13的阈值之后，误差检测信号ERN也从非活动电平连续地变为有效电平。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2004023395A

公开(公告)日：2004-01-22

申请号：JP2002174684

申请日：2002-06-14

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KISHII TATSUYA

IPC: H03G3/02

Abstract: PROBLEM TO BE SOLVED: To provide a gain control circuit for preventing malfunctions caused by external noises and to provide an electronic volume circuit.
SOLUTION: The gain control circuit includes: register means (124, 130, 132) for storing and latching sound volume setting data to set a sound volume of an input audio signal; and control means (136, 134) for outputting volume data to adjust the sound volume of the input audio signal in response to the sound volume setting data latched in the register means. The control means outputs a value not causing abnormality operations as the volume data when the sound volume setting data latched in the register means indicate an extreme value.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003229736A

公开(公告)日：2003-08-15

申请号：JP2002027368

申请日：2002-02-04

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA ,  NORO MASAO

IPC: H03G3/12

Abstract: PROBLEM TO BE SOLVED: To provide a gain control circuit which can input a signal over a power supply voltage and can vary the setting range of the gain. SOLUTION: The gain control circuit is operated with a single power supply and has an amplifier 30 capable of varying the gain. The gain control circuit has a plurality of input terminals 100 and 101, one ends of each of a plurality of resistance elements R1 and R2 having weighted resistance values are connected to each of a plurality of the input terminals, the other ends of a plurality of the resistance elements are commonly connected, the common connection point is connected to the input side of a variable resistance circuit 12 for varying the gain and the signal can be input to all of a plurality of the input terminals or to a part of a plurality of the input terminals. COPYRIGHT: (C)2003,JPO