公开(公告)号：EP0427930A2

公开(公告)日：1991-05-22

申请号：EP90116543.1

申请日：1990-08-29

Applicant: International Business Machines Corporation

Inventor： Bassous, Ernest ,  Blum, Joseph M. ,  Chan, Kevin K. ,  Lamberti, Angela C.

IPC: G03F1/14

CPC classification number: B81C1/00158 ,  B81C2201/0104 ,  B81C2201/0136 ,  B81C2201/053 ,  B81C2203/019 ,  G01L9/0042 ,  G03F1/22 ,  Y10S438/977

Abstract: The method of fabrication of a monolithic silicon membrane structure in which the membrane and its supporting framework are constructed from a single ultra thick body of silicon. The fabrication sequence includes the steps of providing a doped membrane layer on the silicon body, forming an apertured mask on the silicon body, and removal of an unwanted silicon region by mechanical grinding and chemical etching to provide a well opening in the silicon body terminating in the doped membrane.

Abstract translation: 制造单片硅膜结构的方法，其中膜及其支撑框架由单个超厚体硅构成。 制造顺序包括以下步骤：在硅体上提供掺杂的膜层，在硅体上形成孔径掩模，并通过机械研磨和化学蚀刻去除不想要的硅区域，以在硅体中终止孔 掺杂膜。

公开(公告)号：WO2015050761A1

公开(公告)日：2015-04-09

申请号：PCT/US2014/057220

申请日：2014-09-24

Applicant: CAVENDISH KINETICS, INC

Inventor： RENAULT, Mickael ,  JOSHI, Vikram ,  VAN KAMPEN, Robertus Petrus ,  MAGUIRE, Thomas L. ,  KNIPE, Richard L.

IPC: H01H59/00 ,  H01G5/16

CPC classification number: H01G5/16 ,  B81B3/0086 ,  B81B2201/0221 ,  B81B2203/04 ,  B81C1/00166 ,  B81C2201/0104 ,  B81C2201/0109 ,  H01G5/011 ,  H01H59/0009

Abstract: The present invention generally relates to a MEMS device and a method of manufacture thereof. The RF electrode, and hence, the dielectric layer thereover, has a curved upper surface that substantially matches the contact area of the bottom surface of the movable plate. As such, the movable plate is able to have good contact with the dielectric layer and thus, good capacitance is achieved.

Abstract translation: 本发明一般涉及一种MEMS器件及其制造方法。 RF电极，因此其上的介电层具有基本上匹配可动板的底表面的接触面积的弯曲的上表面。 因此，可移动板能够与电介质层良好的接触，从而实现良好的电容。

公开(公告)号：WO2006128953A3

公开(公告)日：2007-02-01

申请号：PCT/FI2006000168

申请日：2006-05-30

Applicant: OKMETIC OYJ ,  LEMPINEN VESA-PEKKA ,  MAEKINEN JARI ,  TILLI MARKKU

Inventor： LEMPINEN VESA-PEKKA ,  MAEKINEN JARI ,  TILLI MARKKU

IPC: B81C1/00

CPC classification number: B81C1/00626 ,  B81B2203/0127 ,  B81C2201/0104 ,  Y10T428/24479

Abstract: A method for thinning a wafer layer to a predetermined thickness comprises two phases of thinning. A first thinning phase and a second thinning phase, wherein the first thinning phase is a preparatory thinning phase and the second thinning phase is a final thinning phase, so performed that the structure comprising silicon meets as thinned the final thickness as predetermined. Such thinned layer in a wafer for instance, can be used in a sensor to be used in normal sized, micromechanical or even nano-sized devices for the device specific sensing applications in electro-mechanical devices.

Abstract translation: 将晶片薄层化为预定厚度的方法包括两个稀化阶段。 第一稀化相和第二稀化相，其中所述第一稀化相是预备性稀化相，并且所述第二稀化相是最终稀化相，因此执行包括硅的结构使预定的最终厚度变薄。 例如，晶片中的这种薄化层可以用在传感器中，以用于在机电装置中用于器件特定感测应用的正常尺寸，微机械或甚至纳米尺寸的装置中。

公开(公告)号：WO2005065436A3

公开(公告)日：2006-04-06

申请号：PCT/US2005000086

申请日：2005-01-03

Applicant: MICROFABRICA INC ,  KUMAR ANANDA H ,  COHEN ADAM L ,  LOCKARD MICHAEL S

Inventor： KUMAR ANANDA H ,  COHEN ADAM L ,  LOCKARD MICHAEL S

IPC: B05D1/38 ,  C08K3/00 ,  C25D3/30 ,  C25D3/38 ,  C25D3/48 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/288 ,  H01L21/301 ,  H01L21/302 ,  H01L21/4763 ,  H01L21/768 ,  B24B53/00

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (98) (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture (292, 294, 296, 298) that ensures precise heights of deposited materials relative to an initial surface of a substrate (82), relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine (408).

Abstract translation: 本发明的一些实施例提供了用于电化学制造多层结构（98）（例如中尺度或微结构）的方法和装置，其具有改进的端点检测和在电化学制造过程中被平坦化的材料（例如层）的并行维护。 一些方法涉及在平坦化期间使用夹具，其确保材料的平面化平面平行于给定公差内的其它沉积平面。 一些方法涉及使用端点检测固定装置（292,294,296,298），其相对于第一沉积层相对于衬底（82）的初始表面或相对于某些其它材料确保沉积材料的精确高度 在制造过程中形成的层。 在一些实施例中，平面化可以通过研磨发生，而其他实施例可以使用金刚石切片机（408）。

公开(公告)号：WO2005065430A3

公开(公告)日：2005-11-03

申请号：PCT/US2005000165

申请日：2005-01-03

Applicant: MICROFABRICA INC ,  COHEN ADAM L ,  FRODIS URI ,  LOCKARD MICHAEL S ,  KUMAR ANANDA H ,  ZHANG GANG ,  SMALLEY DENNIS R

Inventor： COHEN ADAM L ,  FRODIS URI ,  LOCKARD MICHAEL S ,  KUMAR ANANDA H ,  ZHANG GANG ,  SMALLEY DENNIS R

IPC: B05D1/38 ,  C08K3/00 ,  C25D3/30 ,  C25D3/38 ,  C25D3/48 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/288 ,  H01L21/301 ,  H01L21/302 ,  H01L21/4763 ,  H01L21/768

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures are disclosed which include the use of diamond machining (e.g. fly cutting or turning) to planarize layers. Some embodiments focus on systems of sacrificial and structural materials which are useful in Electrochemical fabrication and which can be diamond machined with minimal tool wear (e.g. Ni-P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn, and Au and Sn-Pb), where the first material or materials are the structural materials and the second is the sacrificial material). Some embodiments focus on methods for reducing tool wear when using diamond machining to planarize structures being electrochemically fabricated using difficult-to-machine materials (e.g. by depositing difficult to machine material selectively and potentially with little excess plating thickness, and/or pre-machining depositions to within a small increment of desired surface level (e.g. using lapping or a rough cutting operation) and then using diamond fly cutting to complete the process, and/or forming structures or portions of structures from thin walled regions of hard-to-machine materials as opposed to wide solid regions of structural material.

Abstract translation: 公开了用于形成单层和多层中尺度和微尺度结构的电化学制造方法，其包括使用金刚石机械加工（例如飞切或车削）来平面化层。 一些实施例集中于可用于电化学制造的牺牲和结构材料系统，并且该系统可以以最小的工具磨损进行金刚石加工（例如，Ni-P和Cu，Au和Cu，Cu和Sn，Au和Cu，Au和Sn， 以及Au和Sn-Pb），其中第一种或多种材料是结构材料，第二种是牺牲材料）。 一些实施例集中于减少使用金刚石加工来平坦化使用难加工材料电化学制造的结构时的工具磨损的方法（例如，通过选择性沉积困难的机械材料并且可能几乎没有过量的电镀厚度，和/或预加工沉积 在期望的表面水平的小增量内（例如使用研磨或粗切割操作），然后使用金刚石飞切来完成该过程，和/或从难加工材料的薄壁区域形成结构或部分结构 而不是结构材料的广阔固体区域。

公开(公告)号：EP3259134B1

公开(公告)日：2018-08-08

申请号：EP16702736.6

申请日：2016-02-03

Applicant: Memjet Technology Limited

Inventor： NORTH, Angus ,  O'REILLY, Ronan ,  MCAVOY, Gregory

IPC: B41J2/16 ,  B81C1/00

CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

公开(公告)号：EP1893526B1

公开(公告)日：2017-10-18

申请号：EP06743536.2

申请日：2006-05-30

Applicant: OKMETIC OYJ

Inventor： LEMPINEN, Vesa-Pekka ,  MÄKINEN, Jari ,  TILLI, Markku

IPC: B81C1/00

CPC classification number: B81C1/00626 ,  B81B2203/0127 ,  B81C2201/0104 ,  Y10T428/24479

公开(公告)号：EP2219215A4

公开(公告)日：2014-08-06

申请号：EP08864653

申请日：2008-12-12

Applicant: FUJIKURA LTD

Inventor： YAMAMOTO SATOSHI ,  HASHIMOTO HIROKAZU

IPC: H01L23/02 ,  B81C1/00 ,  H01L27/14 ,  H01L27/146 ,  H01L29/84

CPC classification number: B81C1/00317 ,  B81C2201/0104 ,  B81C2201/0108 ,  B81C2201/0125 ,  B81C2203/0118 ,  B81C2203/0145 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1362827B1

公开(公告)日：2008-09-03

申请号：EP02076937.8

申请日：2002-05-16

Applicant: Micronit Microfluidics B.V.

Inventor： Schlautmann, Stefan ,  Gardeniers, Johannes Gerardus Elisabeth ,  Van den Berg, Albert

IPC: B81B1/00 ,  B81C1/00

CPC classification number: B81C1/00119 ,  B01L3/502707 ,  B01L2200/10 ,  B01L2300/0874 ,  B01L2300/0883 ,  B01L2300/0887 ,  B01L2400/0418 ,  B81B2201/0214 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C2201/0104 ,  G01N33/48707 ,  Y10T137/2191

Abstract: The present invention relates to a method of fabricating a microfluidic device including at least two substrates provided with a fluid channel, comprising the steps of: a) etching at least a channel and one or more fluid ports in a first and/or a second substrate; b) depositing a first layer on a surface of the second substrate; c) partially removing the first layer in accordance with a predefined geometry; d) depositing a second layer on top of the first layer and the substrate surface; e) planarizing the second layer so as to smooth the upper surface thereof; f) aligning the first and second substrate; g) bonding the first substrate on the planarized second layer of the second substrate.

公开(公告)号：EP1893526A2

公开(公告)日：2008-03-05

申请号：EP06743536.2

申请日：2006-05-30

Applicant: OKMETIC OYJ

Inventor： LEMPINEN, Vesa-Pekka ,  MÄKINEN, Jari ,  TILLI, Markku

IPC: B81C1/00

CPC classification number: B81C1/00626 ,  B81B2203/0127 ,  B81C2201/0104 ,  Y10T428/24479

Abstract: A method for thinning a wafer layer to a predetermined thickness comprises two phases of thinning. A first thinning phase and a second thinning phase, wherein the first thinning phase is a preparatory thinning phase and the second thinning phase is a final thinning phase, so performed that the structure comprising silicon meets as thinned the final thickness as predetermined. Such thinned layer in a wafer for instance, can be used in a sensor to be used in normal sized, micromechanical or even nano-sized devices for the device specific sensing applications in electro-mechanical devices.

Abstract translation: 用于将晶片层减薄到预定厚度的方法包括两个减薄阶段。 第一薄化阶段和第二薄化阶段，其中第一薄化阶段是预备薄化阶段，并且第二薄化阶段是最终薄化阶段，从而执行使得包含硅的结构按照预定薄化最终厚度。 例如晶片中的这种薄化层可以用于传感器中，以用于正常尺寸，微机械或甚至纳米尺寸的器件，用于机电装置中的器件特定感测应用。