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    MEMS AND METHOD OF MANUFACTURING THE SAME
    34.
    发明申请
    MEMS AND METHOD OF MANUFACTURING THE SAME 有权
    MEMS及其制造方法

    公开(公告)号：US20120228726A1

    公开(公告)日：2012-09-13

    申请号：US13413889

    申请日：2012-03-07

    Applicant: Tomohiro SAITO

    Inventor： Tomohiro SAITO

    IPC: H01L29/84 ,  H01L21/02

    CPC classification number: H01G5/18 ,  B81B2201/018 ,  B81B2201/0221 ,  B81B2203/0109 ,  B81C1/00611 ,  B81C2201/0126

    Abstract: According to one embodiment, a MEMS includes a first electrode, a first auxiliary structure and a second electrode. The first electrode is provided on a substrate. The first auxiliary structure is provided on the substrate and adjacent to the first electrode. The first auxiliary structure is in an electrically floating state. The second electrode is provided above the first electrode and the first auxiliary structure,

    Abstract translation: 根据一个实施例，MEMS包括第一电极，第一辅助结构和第二电极。 第一电极设置在基板上。 第一辅助结构设置在基板上并与第一电极相邻。 第一辅助结构处于电浮动状态。 第二电极设置在第一电极和第一辅助结构之上，

    Polysilicon Planarization Solution for Planarizing Low Temperature Poly-Silicon Thin Film Panels
    35.
    发明申请
    Polysilicon Planarization Solution for Planarizing Low Temperature Poly-Silicon Thin Film Panels 审中-公开
    用于平面化低温多晶硅薄膜面板的多晶硅平面化解决方案

    公开(公告)号：US20100126961A1

    公开(公告)日：2010-05-27

    申请号：US12596921

    申请日：2008-02-19

    Applicant: Sang In Kim ,  Seong Jin Hong

    Inventor： Sang In Kim ,  Seong Jin Hong

    IPC: C23F1/32 ,  C09K13/02

    CPC classification number: B81C1/00611 ,  B81C2201/0126 ,  C09K13/02 ,  H01L21/32134 ,  H01L29/6675

    Abstract: A highly aqueous, strongly basic planarizing solution and a process for its use to reducing or essentially eliminating protrusions or projections extending generally upwardly from a generally planar surface of polysilicon film produced by Low Temperature Poly Si (LTPS) annealing a film of amorphous silicon deposited on a substrate; the process including contacting the surface of the generally planar polysilicon film with the highly aqueous, strongly basic solution for a time sufficient to selectively etch the protrusions or projections from the surface of the generally planar polysilicon film without any significant etching of the generally planar polysilicon film, said highly aqueous, strongly basic solution being a solution having a pH of 12 or higher and comprising water, at least one strong base, and at least one etch rate control agent.

    Abstract translation: 高度水性，强碱性的平面化溶液和用于减少或基本上消除从通过低温多晶硅（LTPS）生产的多晶硅膜的大致平坦表面大致向上延伸的突起或突起的方法，退火沉积在非晶硅上的非晶硅膜 底物; 该方法包括使大体上平坦的多晶硅膜的表面与高水溶液，强碱性溶液接触一段时间，足以从大体上平坦的多晶硅膜的表面选择性地蚀刻突起或突起，而无需大致平坦的多晶硅膜的显着蚀刻 所述高含水强碱性溶液是pH为12或更高的溶液，其包含水，至少一种强碱和至少一种蚀刻速率控制剂。

    Method of smoothing a trench sidewall after a deep trench silicon etch process
    36.
    发明申请
    Method of smoothing a trench sidewall after a deep trench silicon etch process 失效
    在深沟槽硅蚀刻工艺之后平滑沟槽侧壁的方法

    公开(公告)号：US20030211752A1

    公开(公告)日：2003-11-13

    申请号：US10137543

    申请日：2002-05-01

    Inventor： Michael Rattner ,  Jeffrey D. Chinn

    IPC: H01L021/302 ,  H01L021/461

    CPC classification number: B81C1/00611 ,  B81B2203/033 ,  B81C2201/0126 ,  B81C2201/0178 ,  H01L21/3065 ,  H01L21/30655

    Abstract: Disclosed herein is a method of smoothing a trench sidewall after a deep trench silicon etch process which minimizes sidewall scalloping present after the silicon trench etch. The method comprises exposing the silicon trench sidewall to a plasma generated from a fluorine-containing gas, at a process chamber pressure within the range of about 1 mTorr to about 30 mTorr, for a time period within the range of about 10 seconds to about 600 seconds. A substrate bias voltage within the range of about null10 V to about null40 V is applied during the performance of the post-etch treatment method of the invention.

    Abstract translation: 这里公开了一种在深沟槽硅蚀刻工艺之后平滑沟槽侧壁的方法，其最小化在硅沟槽蚀刻之后存在的侧壁扇形。 该方法包括将硅沟槽侧壁暴露于在约1mTorr至约30mTorr范围内的处理室压力下从含氟气体产生的等离子体，时间范围为约10秒至约600 秒。 在本发明的蚀刻后处理方法的执行期间，施加约-10V至约-40V范围内的衬底偏置电压。

    Planarizing process for field emitter displays and other electron source applications
    37.
    发明授权
    Planarizing process for field emitter displays and other electron source applications 失效
    场发射显示器和其他电子源应用的平面化处理

    公开(公告)号：US5688158A

    公开(公告)日：1997-11-18

    申请号：US519121

    申请日：1995-08-24

    Applicant: Gary W. Jones ,  Steven M. Zimmerman ,  Susan K. Schwartz Jones ,  Michael J. Costa ,  Jeffrey A. Silvernail

    Inventor： Gary W. Jones ,  Steven M. Zimmerman ,  Susan K. Schwartz Jones ,  Michael J. Costa ,  Jeffrey A. Silvernail

    IPC: B81C1/00 ,  H01J9/02

    CPC classification number: B81C1/00611 ,  H01J9/025 ,  B81C2201/0126

    Abstract: A planarization method for use during manufacture of a microelectronic field emitter device, comprising applying a glass frit slurry including glass particles in a removable base, and subsequently baking to liquify the frit. The invention relates in another aspect to a method of making a microelectronic field emitter device, comprising the steps of: applying a patterned layer of liftoff profile resist over a substrate to define emitter conductor locations; employing the patterned resist layer to form trenches in the substrate at the emitter conductor locations; depositing emitter conductor metal in the trenches and over the patterned resist layer; removing the patterned resist layer; depositing a current limiter layer over the conductors and substrate areas between trenches; depositing a layer of emitter material; pattern masking and etching the layer of emitter material to form emitter structures; depositing gate dielectric; applying a patterned layer of liftoff profile resist over the gate dielectric; evaporating gate metal; and removing the patterned resist layer to define gate electrodes.

    Abstract translation: 一种在制造微电子场发射器件期间使用的平面化方法，包括将包括玻璃颗粒的玻璃料浆料涂覆在可移除的基底中，随后烘焙以熔化玻璃料。 本发明在另一方面涉及一种制造微电子场发射器件的方法，包括以下步骤：在衬底上施加图案化的剥离轮廓抗蚀剂层以限定发射体导体位置; 使用图案化的抗蚀剂层在发射极导体位置处在衬底中形成沟槽; 将发射极导体金属沉积在沟槽中和图案化抗蚀剂层上方; 去除图案化的抗蚀剂层; 在沟槽之间的导体和衬底区域上沉积限流器层; 沉积一层发射体材料; 图案掩蔽和蚀刻发射体材料层以形成发射体结构; 沉积栅电介质; 在栅极电介质上施加图案化的剥离轮廓抗蚀剂层; 蒸发栅极金属; 并去除图案化的抗蚀剂层以限定栅电极。

    GLASARTIGES FLÄCHENSUBSTRAT, SEINE VERWENDUNG UND VERFAHREN ZU SEINER HERSTELLUNG
    39.
    发明授权
    GLASARTIGES FLÄCHENSUBSTRAT, SEINE VERWENDUNG UND VERFAHREN ZU SEINER HERSTELLUNG 有权
    像玻璃一样面积的基板，其用途及其制造方法

    公开(公告)号：EP1535315B1

    公开(公告)日：2010-11-24

    申请号：EP03775135.1

    申请日：2003-08-22

    Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

    Inventor： QUENZER, Hans-Joachim ,  SCHULZ, Arne, Veit ,  MERZ, Peter

    IPC: H01L21/20 ,  B81C1/00 ,  C03B19/02 ,  C03B23/02

    CPC classification number: B81C1/00611 ,  B81C2201/0126 ,  C03B19/02 ,  C03B23/02

    Abstract: Disclosed is a method for structuring a planar substrate made of a glass-type material, which is characterized by the following steps: - the thickness of the planar semiconductor substrate is reduced within at least one surface area thereof so as to obtain a surface area that is raised relative to the surface areas having a reduced thickness; - the raised surface area of the planar semiconductor substrate is structured by locally removing material in a mechanical manner so as to introduce recesses within the raised surface area; - the structured surface of the planar semiconductor substrate is connected to the glass-type planar substrate such that the glass-type planar substrate at least partly covers the surface area having a reduced thickness; - the connected planar substrates are heated up such that the glass-type planar substrate which covers the surface area having a reduced thickness forms a fluid-tight connection along with the surface area having a reduced thickness in a first heating phase which is carried out at negative pressure conditions, the planar substrate covering the recesses in a fluid-tight manner at negative pressure conditions, whereupon at least some areas of the glass-type material flow into the recesses of the structured surface of the planar semiconductor substrate in a second heating phase. Also disclosed are a glass-type planar substrate and the use thereof.

    POLYSILICON PLANARIZATION SOLUTION FOR PLANARIZING LOW TEMPERATURE POLYSILICON THIN FILM PANELS
    40.
    发明公开
    POLYSILICON PLANARIZATION SOLUTION FOR PLANARIZING LOW TEMPERATURE POLYSILICON THIN FILM PANELS 审中-公开
    多晶硅平面化的解决方案，平坦化低温薄膜木板多晶硅

    公开(公告)号：EP2147462A2

    公开(公告)日：2010-01-27

    申请号：EP08725768.9

    申请日：2008-02-19

    Applicant: Mallinckrodt Baker, Inc.

    Inventor： KIM, Sang In ,  HONG, Seong Jin

    IPC: H01L21/311 ,  H01L21/3213 ,  C09K13/02

    CPC classification number: B81C1/00611 ,  B81C2201/0126 ,  C09K13/02 ,  H01L21/32134 ,  H01L29/6675

    Abstract: A highly aqueous, strongly basic planarizing solution and a process for its use to reducing or essentially eliminating protrusions or projections extending generally upwardly from a generally planar surface of polysilicon film produced by Low Temperature Poly Si (LTPS) annealing a film of amorphous silicon deposited on a substrate; the process including contacting the surface of the generally planar polysilicon film with the highly aqueous, strongly basic solution for a time sufficient to selectively etch the protrusions or projections from the surface of the generally planar polysilicon film without any significant etching of the generally planar polysilicon film, said highly aqueous, strongly basic solution being a solution having a pH of 12 or higher and comprising water, at least one strong base, and at least one etch rate control agent.

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