公开(公告)号：US20030110867A1

公开(公告)日：2003-06-19

申请号：US10268711

申请日：2002-10-10

Inventor： Hans Artmann ,  Thorsten Pannek

IPC: G01F001/56

CPC classification number: B81C1/0069 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  B81C2201/0139

Abstract: In a method for producing a diaphragm sensor unit having a semiconductor material substrate, a flat diaphragm and an insulating well for thermal insulation below the diaphragm are generated, for the formation of sensor element structures for at least one sensor. The substrate, made of semiconductor material, in a specified region, which defines sensor element structures, receives a deliberately different doping from the surrounding semiconductor material, that porous semiconductor material is generated from semiconductor material sections between the regions distinguished by doping, and semiconductor material in the well region under semiconductor is rendered porous and under parts of the sensor element structure is removed and/or rendered porous.

Abstract translation: 在制造具有半导体材料基板的隔膜传感器单元的方法中，产生用于形成用于至少一个传感器的传感器元件结构的隔膜下方的平坦隔膜和隔热绝缘孔。 由限定传感器元件结构的特定区域中的由半导体材料制成的衬底接收与周围半导体材料的故意不同的掺杂，多孔半导体材料是由掺杂区域之间的半导体材料部分和半导体材料 在半导体中的阱区域被多孔化并且在传感器元件结构的部分被去除和/或变得多孔的情况下。

公开(公告)号：US20180301344A1

公开(公告)日：2018-10-18

申请号：US15986304

申请日：2018-05-22

Applicant: The Board of Trustees of the University of Illinois

Inventor： Lynford Goddard ,  Kaiyuan Wang ,  Chris Edwards ,  Lonna Edwards ,  Xin Yu ,  Gang Logan Liu ,  Samuel Washington ,  Shailendra Srivastava ,  Terry Koker ,  Julianne Lee ,  Catherine Britt Carlson

IPC: H01L21/306 ,  H01L31/0236 ,  C25F3/14 ,  H01L31/0232 ,  H01L21/66 ,  G01B11/24

CPC classification number: H01L21/30604 ,  B81C1/00103 ,  B81C1/00111 ,  B81C1/00119 ,  B81C1/00214 ,  B81C1/00484 ,  B81C1/00539 ,  B81C1/00595 ,  B81C2201/0114 ,  B81C2201/0139 ,  B81C2201/0157 ,  C25F3/12 ,  C25F3/14 ,  G01B11/2441 ,  H01L21/30617 ,  H01L21/3063 ,  H01L21/76886 ,  H01L22/12 ,  H01L31/02327 ,  H01L31/02363

Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.

公开(公告)号：US20150368097A1

公开(公告)日：2015-12-24

申请号：US14838988

申请日：2015-08-28

Applicant: Infineon Technologies AG

Inventor： Andreas Behrendt ,  Kai-Alexander Schreiber ,  Sokratis Sgouridis ,  Martin Zgaga ,  Bernhard Winkler

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00531 ,  B81B3/0021 ,  B81B3/0094 ,  B81B2203/033 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0139 ,  H01L21/3063

Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

Abstract translation: 一种用于在半导体衬底内制造至少一个空腔的方法包括：在半导体衬底的表面在至少一个预定的腔位置干蚀刻半导体衬底，以便获得至少一个临时空腔。 该方法包括在半导体衬底的表面和至少一个临时空腔的空腔表面处沉积关于随后的湿法蚀刻工艺的保护材料。 此外，该方法包括至少在至少一个临时空腔的底部的一部分处去除保护材料以暴露半导体衬底。 接着在至少一个临时腔的底部的暴露部分对半导体衬底进行电化学蚀刻。 还公开了使用这种类型的空腔形成和相应的MEMS的微机械传感器系统的制造方法。

公开(公告)号：US20130270658A1

公开(公告)日：2013-10-17

申请号：US13864762

申请日：2013-04-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Behrendt ,  Kai-Alexander Schreiber ,  Sokratis Sgouridis ,  Martin Zgaga ,  Bernhard Winkler

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00531 ,  B81B3/0021 ,  B81B3/0094 ,  B81B2203/033 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0139 ,  H01L21/3063

Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

公开(公告)号：US07160750B2

公开(公告)日：2007-01-09

申请号：US10473762

申请日：2002-02-21

Applicant: Hubert Benzel ,  Heribert Weber ,  Frank Schaefer

Inventor： Hubert Benzel ,  Heribert Weber ,  Frank Schaefer

IPC: H01L21/00

CPC classification number: B81C1/00047 ,  B81B2201/0278 ,  B81C2201/0115 ,  B81C2201/0139

Abstract: A method for manufacturing a semiconductor component, such as, for example, a multilayer semiconductor component including a micromechanical component, such as, for example, a heat transfer sensor having a semiconductor substrate of silicon, and a sensor region. For inexpensive manufacture of a thermal insulation between the semiconductor substrate and the sensor region a porous layer is provided in the semiconductor component.

Abstract translation: 一种半导体部件的制造方法，例如包括微机械部件的多层半导体部件，例如具有硅的半导体基板的传热传感器和传感器区域。 为了廉价地制造半导体基板和传感器区域之间的绝热，在半导体部件中设置多孔层。

公开(公告)号：US20030127699A1

公开(公告)日：2003-07-10

申请号：US10328661

申请日：2002-12-23

Inventor： Hans Artmann ,  Thorsten Pannek

IPC: H01L021/00

CPC classification number: B81C1/0069 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  B81C2201/0139

Abstract: In a method for producing a diaphragm sensor unit having a semiconductor material substrate, a flat diaphragm and an insulating well for thermal insulation below the diaphragm are generated, for the formation of sensor element structures for at least one sensor. The substrate, made of semiconductor material, in a specified region, which defines sensor element structures, receives a deliberately different doping from the surrounding semiconductor material, that porous semiconductor material is generated from semiconductor material sections between the regions distinguished by doping, and semiconductor material in the well region under semiconductor is rendered porous and under parts of the sensor element structure is removed and/or rendered porous.

Abstract translation: 在制造具有半导体材料基板的隔膜传感器单元的方法中，产生用于形成用于至少一个传感器的传感器元件结构的隔膜下方的平坦隔膜和隔热绝缘孔。 由限定传感器元件结构的特定区域中的由半导体材料制成的衬底接收与周围半导体材料的故意不同的掺杂，多孔半导体材料是由掺杂区域之间的半导体材料部分和半导体材料 在半导体中的阱区域被多孔化并且在传感器元件结构的部分被去除和/或变得多孔的情况下。

公开(公告)号：US20020132101A1

公开(公告)日：2002-09-19

申请号：US10104749

申请日：2002-03-22

Applicant: The Penn State Research Foundation

Inventor： Stephen J. Fonash ,  Alikaan Kalkan ,  Sanghoon Bae

IPC: B32B003/26

CPC classification number: B81C1/0038 ,  B81C1/00047 ,  B81C2201/0115 ,  B81C2201/0139 ,  B81C2201/018 ,  C23C16/24 ,  C23C16/511 ,  G01N21/17 ,  G01N27/121 ,  G01N27/44717 ,  G01N30/6095 ,  H01J49/0418 ,  Y10T428/24174 ,  Y10T428/249953

Abstract: A novel porous film is disclosed comprising a network of silicon columns in a continuous void which may be fabricated using high density plasma deposition at low temperatures, i.e., less than about 250 null C. This silicon film is a two-dimensional nano-sized array of rodlike columns. This void-column morphology can be controlled with deposition conditions and the porosity can be varied up to 90%. The simultaneous use of low temperature deposition and etching in the plasma approach utilized, allows for the unique opportunity of obtaining columnar structure, a continuous void, and polycrystalline column composition at the same time. Unique devices may be fabricated using this porous continuous film by plasma deposition of this film on a glass, metal foil, insulator or plastic substrates.

Abstract translation: 公开了一种新颖的多孔膜，其包括在连续空隙中的硅柱网络，其可以在低温下（即小于约250℃）下使用高密度等离子体沉积来制造。该硅膜是二维纳米尺寸阵列 的棒状柱。 这种空隙柱形态可以用沉积条件控制，并且孔隙率可以变化高达90％。 在所采用的等离子体方法中同时使用低温沉积和蚀刻允许在同时获得柱状结构，连续空隙和多晶柱组成的独特机会。 可以使用这种多孔连续膜通过将该膜等离子体沉积在玻璃，金属箔，绝缘体或塑料基底上来制造独特的器件。

公开(公告)号：WO2007027907A3

公开(公告)日：2009-05-07

申请号：PCT/US2006034051

申请日：2006-09-01

Applicant: UNIV COLUMBIA ,  VON GUTFELD ROBERT J ,  WEST ALAN C

Inventor： VON GUTFELD ROBERT J ,  WEST ALAN C

IPC: C23F1/00 ,  C25F3/02 ,  C25F7/00

CPC classification number: C25F3/02 ,  B81C1/00571 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/0142 ,  C23F1/02 ,  C23F1/08 ,  H05K3/068 ,  H05K2203/1105 ,  H05K2203/1115

Abstract: Systems and methods for etching topographic features in non- crystalline or metallic substrates are provided. A protective material is placed and patterned on a surface of the substrate to define exposed and protected regions of the substrate for etching in a liquid etchant having etching rates that are thermally activated. A nonuniform temperature profile is imposed on the substrate so that the temperatures and hence the etching rates at surfaces in the exposed regions are higher than those in the protected regions. Arrangements for imposing the nonuniform temperature profile include heating designated portions of the substrate with light radiation. Alternatively, the non-uniform temperature profile is developed as etching progresses by passing current pulses through the substrate in a manner that causes geometrically non-uniform heating of the substrate.

Abstract translation: 提供用于蚀刻非晶体或金属基底中的地形特征的系统和方法。 保护材料被放置并图案化在衬底的表面上以限定衬底的暴露和保护区域，以在具有热激活蚀刻速率的液体蚀刻剂中蚀刻。 对基板施加不均匀的温度曲线，使得暴露区域中的表面的温度和蚀刻速率高于受保护区域中的温度。 施加不均匀温度分布的布置包括用光辐射加热衬底的指定部分。 或者，当通过使电流脉冲以导致衬底的几何不均匀加热的方式通过衬底时蚀刻进行蚀刻而开发不均匀的温度分布。

公开(公告)号：WO2007027907A2

公开(公告)日：2007-03-08

申请号：PCT/US2006/034051

申请日：2006-09-01

Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK ,  VON GUTFELD, Robert, J. ,  WEST, Alan, C.

Inventor： VON GUTFELD, Robert, J. ,  WEST, Alan, C.

IPC: B05D5/04

CPC classification number: C25F3/02 ,  B81C1/00571 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/0142 ,  C23F1/02 ,  C23F1/08 ,  H05K3/068 ,  H05K2203/1105 ,  H05K2203/1115

Abstract: Systems and methods for etching topographic features in non- crystalline or metallic substrates are provided. A protective material is placed and patterned on a surface of the substrate to define exposed and protected regions of the substrate for etching in a liquid etchant having etching rates that are thermally activated. A nonuniform temperature profile is imposed on the substrate so that the temperatures and hence the etching rates at surfaces in the exposed regions are higher than those in the protected regions. Arrangements for imposing the nonuniform temperature profile include heating designated portions of the substrate with light radiation. Alternatively, the non-uniform temperature profile is developed as etching progresses by passing current pulses through the substrate in a manner that causes geometrically non-uniform heating of the substrate.

Abstract translation: 提供用于蚀刻非晶体或金属基底中的地形特征的系统和方法。 保护材料被放置并图案化在衬底的表面上以限定衬底的暴露和保护区域，以在具有热激活蚀刻速率的液体蚀刻剂中蚀刻。 对基板施加不均匀的温度曲线，使得暴露区域中的表面的温度和蚀刻速率高于受保护区域中的温度。 施加不均匀温度分布的布置包括用光辐射加热衬底的指定部分。 或者，当通过使电流脉冲以导致衬底的几何不均匀加热的方式通过衬底时蚀刻进行蚀刻而开发不均匀的温度分布。

公开(公告)号：EP1258034B1

公开(公告)日：2008-03-26

申请号：EP01902922.2

申请日：2001-01-26

Applicant: Cree Sweden AB

Inventor： HARRIS, Christopher ,  KONSTANTINOV, Andrei ,  ADAS, Christian ,  KARLSSON, Stefan ,  HÖRMAN, Thomas

IPC: H01L21/3063 ,  B81C1/00 ,  H01L41/22

CPC classification number: B81C1/00539 ,  B81C2201/0114 ,  B81C2201/0139 ,  H01L21/0475

Abstract: The invention relates to a method for selective etching of SiC, the etching being carried out by applying a positive potential to a layer (3; 8) of p-type SiC being in contact with an etching solution containing fluorine ions and having an oxidising effect on SiC. The invention also relates to a method for producing a SiC micro structure having free hanging parts (i.e. diaphragm, cantilever or beam) on a SiC-substrate, a method for producing a MEMS device of SiC having a free hanging structure, and a method for producing a piezo-resistive pressure sensor comprising the step of applying a positive potential to a layer (8) of p-type SiC being in contact with an etching solution containing fluorine ions and having an oxidising effect on SiC.