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    CIRCUIT STRUCTURE AND PROCESS THEREOF
    41.
    发明申请
    CIRCUIT STRUCTURE AND PROCESS THEREOF 有权
    电路结构及其过程

    公开(公告)号：US20080179744A1

    公开(公告)日：2008-07-31

    申请号：US11739515

    申请日：2007-04-24

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H01L23/48

    CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

    Abstract: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface of the first dielectric layer away from the first via pad and connecting to one end of the first conductive via. The circuit structure further has a second dielectric layer disposed over the surface of the first dielectric layer where the independent via pad is disposed, a second conductive via passing through the second dielectric layer and connecting to the independent via pad, and a second circuit pattern embedded in the second dielectric layer, located at a surface thereof away from the independent via pad, and having a second via pad connected to the second conductive via.

    Abstract translation: 电路结构具有第一电介质层，第一电路图案，其嵌入在第一电介质层中并且具有第一通孔焊盘，穿过第一电介质层并连接到第一通孔焊盘的第一导电通孔和设置在第一电介质层上的独立通孔焊盘 在第一电介质层的远离第一通孔焊盘的表面上并连接到第一导电通孔的一端。 电路结构还具有设置在第一电介质层的表面上的第二电介质层，其中设置独立通孔焊盘，通过第二介电层并连接到独立通孔焊盘的第二导电通孔和嵌入的第二电路图案 在第二电介质层中，位于其远离独立通孔焊盘的表面，并且具有连接到第二导电通孔的第二通孔焊盘。

    Method of manufacturing an embedded wiring board
    44.
    发明授权
    Method of manufacturing an embedded wiring board 有权
    嵌入式布线板的制造方法

    公开(公告)号：US09131614B2

    公开(公告)日：2015-09-08

    申请号：US13620431

    申请日：2012-09-14

    Applicant: Cheng-Po Yu ,  Chai-Liang Hsu

    Inventor： Cheng-Po Yu ,  Chai-Liang Hsu

    IPC: H05K3/02 ,  H05K3/10 ,  H05K3/18 ,  H05K3/42

    CPC classification number: H05K3/107 ,  H05K3/181 ,  H05K3/422 ,  H05K2201/0376

    Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed. The activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

    Abstract translation: 提供了一种用于制造嵌入式布线板的方法。 形成激活绝缘层。 激活绝缘层包括多个催化剂颗粒，并且覆盖第一布线层。 在活化绝缘层上形成凹版图案和部分露出第一布线层的至少一个盲孔，其中一些催化剂颗粒被活化并以凹版图案和盲孔曝光。 将激活绝缘层浸入第一化学镀溶液中，并通过化学镀在盲孔中形成固体导电柱。 在形成固体导电柱之后，将激活绝缘层浸入第二化学镀溶液中，并且通过无电解电镀在凹版图案中形成第二布线层。 第一化学镀液和第二化学镀液的成分不同。

    CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF
    45.
    发明申请
    CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    电路结构及其制造方法

    公开(公告)号：US20140041919A1

    公开(公告)日：2014-02-13

    申请号：US13615722

    申请日：2012-09-14

    Applicant: Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

    Inventor： Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

    IPC: H05K1/11 ,  H05K3/10

    CPC classification number: H05K1/0221 ,  H05K3/4644 ,  Y10T29/49155

    Abstract: A circuit structure includes an inner circuit layer, a first and a second dielectric layers, a first and a second conductive material layers, and a second and a third conductive layers. The first dielectric layer covers a first conductive layer of the inner circuit layer and has a first surface and first circuit grooves. The first conductive material layer is disposed inside the first circuit grooves. The second conductive layer is disposed on the first surface and includes a signal trace and at least two reference traces. The second dielectric layer covers the first surface and the second conductive layer and has a second surface and second circuit grooves. Widths of the first and the second circuit grooves are smaller than that of the reference traces. The second conductive material layer is disposed inside the second circuit grooves. The third conductive layer is disposed on the second surface.

    Abstract translation: 电路结构包括内部电路层，第一和第二电介质层，第一和第二导电材料层以及第二和第三导电层。 第一电介质层覆盖内电路层的第一导电层，并具有第一表面和第一电路槽。 第一导电材料层设置在第一电路槽的内部。 第二导电层设置在第一表面上并且包括信号迹线和至少两个参考迹线。 第二电介质层覆盖第一表面和第二导电层，并具有第二表面和第二电路槽。 第一和第二电路槽的宽度小于参考轨迹的宽度。 第二导电材料层设置在第二电路槽的内部。 第三导电层设置在第二表面上。

    CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF
    46.
    发明申请
    CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF 有权
    电路板及其制造方法

    公开(公告)号：US20130327564A1

    公开(公告)日：2013-12-12

    申请号：US13570251

    申请日：2012-08-09

    Applicant: Cheng-Po Yu ,  Shang-Feng Huang ,  Chang-Ming Lee ,  Young-Sheng Bai

    Inventor： Cheng-Po Yu ,  Shang-Feng Huang ,  Chang-Ming Lee ,  Young-Sheng Bai

    IPC: H05K1/11 ,  H05K3/00

    CPC classification number: H05K3/381 ,  H05K3/105 ,  H05K3/108 ,  H05K2201/0215 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/095 ,  H05K2203/1461

    Abstract: A circuit board and a manufacturing method thereof are provided. According to the method, a dielectric layer is formed on a dielectric substrate, and the dielectric layer contains active particles. A surface treatment is performed on a surface of the dielectric first conductive layer is formed on the activated surface of the dielectric layer. A conductive via is formed in the dielectric substrate and the dielectric layer. A patterned mask layer is formed on the first conductive layer, in which the patterned mask layer exposes the conductive via and a part of the first conductive layer. A second conductive layer is formed on the first conductive layer and conductive via exposed by the patterned mask layer. The patterned mask layer and the first conductive layer below the patterned mask layer are removed.

    Abstract translation: 提供一种电路板及其制造方法。 根据该方法，在电介质基板上形成介电层，电介质层含有活性粒子。 在电介质层的活化表面上形成电介质第一导电层的表面进行表面处理。 在电介质基板和电介质层中形成导电通孔。 图案化的掩模层形成在第一导电层上，其中图案化掩模层暴露导电通孔和第一导电层的一部分。 在第一导电层上形成第二导电层，并且由图案化掩模层暴露出导电通路。 图案化掩模层和图案化掩模层下面的第一导电层被去除。

    DISPLAY DEVICE AND LIGHT SENSING SYSTEM
    47.
    发明申请
    DISPLAY DEVICE AND LIGHT SENSING SYSTEM 有权
    显示设备和光感测系统

    公开(公告)号：US20130011576A1

    公开(公告)日：2013-01-10

    申请号：US13620431

    申请日：2012-09-14

    Applicant: CHENG-PO YU ,  CHAI-LIANG HSU

    Inventor： CHENG-PO YU ,  CHAI-LIANG HSU

    IPC: H05K3/10

    CPC classification number: H05K3/107 ,  H05K3/181 ,  H05K3/422 ,  H05K2201/0376

    Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed. The activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

    Abstract translation: 提供了一种用于制造嵌入式布线板的方法。 形成激活绝缘层。 激活绝缘层包括多个催化剂颗粒，并且覆盖第一布线层。 在活化绝缘层上形成凹版图案和部分露出第一布线层的至少一个盲孔，其中一些催化剂颗粒被活化并以凹版图案和盲孔曝光。 将激活绝缘层浸入第一化学镀溶液中，并通过化学镀在盲孔中形成固体导电柱。 在形成固体导电柱之后，将激活绝缘层浸入第二化学镀溶液中，并且通过无电解电镀在凹版图案中形成第二布线层。 第一化学镀液和第二化学镀液的成分不同。

    Method of making a circuit structure of a circuit board
    48.
    发明授权
    Method of making a circuit structure of a circuit board 有权
    制作电路板电路结构的方法

    公开(公告)号：US08166652B2

    公开(公告)日：2012-05-01

    申请号：US12270718

    申请日：2008-11-13

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K3/10

    CPC classification number: H05K3/107 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/061 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0369 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.

    Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。

    Manufacturing method of circuit structure
    49.
    发明授权
    Manufacturing method of circuit structure 有权
    电路结构的制造方法

    公开(公告)号：US08161638B2

    公开(公告)日：2012-04-24

    申请号：US12783806

    申请日：2010-05-20

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H01K3/10

    CPC classification number: H05K3/465 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/184 ,  H05K3/421 ,  H05K3/4661 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1056

    Abstract: A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.

    Abstract translation: 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。

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