Abstract:
A shipping container system comprises an inner liner (1) for insertion into an inner shipping container (15), for insertion into an outer shipping container (16). The inner liner (1) comprises a layer of single- or double-bubble radiant barrier material (13) within a sealed vinyl pouch (21). Between the outer container (6) and the inner container (5) there is furnished at least one spacer tray (3), for providing a partially-surrounding pocket of air in contact with the exterior surface of the inner container (5). During sealing of the pouch (21), a pocket of air is allowed to remain in its interior so that the radiant barrier material (13) floats within the sealed pouch (21). The pockets of air provided allow for maximization of the thermal insulating properties of the system due primarily to the thermal reflective property of the radiant barrier material. The vinyl construction of the pouch material provides a durable protective cover for the radiant barrier material.
Abstract:
An improved method for constructing integrated circuit structures in which a buffer SiO2 layer (203) is used to separate various components comprising ferroelectric materials (208) or platinum (202) is disclosed. The invention prevents interactions between the SiO2 buffer layer (203) and the ferroelectric materials (208). The invention also prevents the cracking in the SiO2 which is commonly observed when the SiO2 layer (203) is deposited directly over a platinum region (202) on the surface of the circuit. The present invention utilizes a buffer layer of material which is substantially inert with respect to the ferroelectric material (208) and which is also an electrical insulator to separate the SiO2 layer (203) from the ferroelectric material (208) and/or the platinum regions (202).
Abstract:
An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentrations between 1% and 8%.
Abstract:
An improved method for constructing integrated circuit structures in which a buffer SiO2 layer is used to separate various components comprising ferroelectric materials or platinum is disclosed. The invention prevents interactions between the SiO2 buffer layer and the ferroelectric materials. The invention also prevents the cracking in the SiO2 which is commonly observed when the SiO2 layer is deposited directly over a platinum region on the surface of the circuit. The present invention utilizes a buffer layer of material which is substantially inert with respect to the ferroelectric material and which is also an electrical insulator to separate the SiO2 layer from the ferroelectric material and/or the platinum regions.
Abstract:
A sense amplifier for comparing the resistance of a reference cell connected to a reference bit line to the resistance of a data cell connected to a data bit line. The amplifier includes a first terminal for connecting the sense amplifier to the reference bit line and a second terminal for connecting the sense amplifier to the data bit line. A reference current to voltage amplifier is connected to the first terminal for generating a reference voltage related to the current flowing through the reference bit line and for maintaining the first terminal at a reference potential when the current flowing through the reference bit line is less than a first current value. A data current to voltage amplifier is connected to the second terminal for generating a data voltage related to the current flowing through the data bit line and for maintaining the second terminal at the reference potential when the current flowing through the data bit line is less than a second current value. A comparitor compares the reference and data voltages. The data current to voltage amplifier includes an operational amplifier for measuring the difference between a potential on a first conductor and the potential on the data bit line. The operational amplifier allows the reference potential to be set at a lower voltage than is available in prior art designs. The invention utilizes a capacitive dividing scheme for pre-charging the bit lines prior to connecting the sense amplifier.
Abstract:
An improved method for constructing integrated circuit structures in which a buffer SiO2 layer is used to separate various components comprising ferroelectric materials or platinum is disclosed. The invention prevents interactions between the SiO2 buffer layer and the ferroelectric materials. The invention also prevents the cracking in the SiO2 which is commonly observed when the SiO2 layer is deposited directly over a platinum region on the surface of the circuit. The present invention utilizes a buffer layer of material which is substantially inert with respect to the ferroelectric material and which is also an electrical insulator to separate the SiO2 layer from the ferroelectric material and/or the platinum regions.
Abstract:
A ferroelectric memory cell for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer by setting the direction of the remnant polarization. The ferroelectric memory cell is designed to store the information at a temperature less than a first temperature. The memory cell includes top and bottom contacts that sandwich the dielectric layer which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400 DEG C. The dielectric layer is encapsulated in an oxygen impermeable material such that the encapsulating layer prevents oxygen from entering or leaving the dielectric layer. One of the contacts is typically includes a platinum electrode. The other contact may include a similar electrode or a semiconductor layer having electrodes spaced apart thereon.
Abstract:
A light activated switching device is disclosed in which the receipt of a light signal is used to switch a light beam between two output ports. The input light beam is reflected from an interface between two regions having different indices of refraction when the light signal is present. The reflected light beam then exits through the first output port. In the absence of the light signal, the two regions have the same index of refraction, and the light beam passes through both regions and exits through the second output port.
Abstract:
A light activated switching device is disclosed in which the receipt of a light signal is used to switch a light beam between two output ports. The input light beam is reflected from an interface between two regions having different indices of refraction when the light signal is present. The reflected light beam then exits through the first output port. In the absence of the light signal, the two regions have the same index of refraction, and the light beam passes through both regions and exits through the second output port.
Abstract:
A method for connecting a silicon substrate to an electrical component via a platinum conductor. The resulting structure may be heated in the presence of oxygen to temperatures in excess of 800 DEG C. without destroying the electrical connection between the silicon substrate and components connected to the platinum conductor. The present invention utilizes a TiN or TiW buffer layer to connect the platinum conductor to the silicon substrate. The buffer layer is deposited as a single crystal on the silicon substrate. The platinum layer is then deposited on the buffer layer. The region of the platinum layer in contact with the buffer layer is also a single crystal.