公开(公告)号：EP0587401A2

公开(公告)日：1994-03-16

申请号：EP93307036.9

申请日：1993-09-07

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Wyborn, Graeme Michael ,  McGee, Christopher ,  Nicholls, Howard Charles

IPC: H01L21/3205 ,  H01L21/90 ,  C23C16/14

CPC classification number: H01L21/28556 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76877 ,  H01L21/76879

Abstract: A method of fabricating a tungsten contact in a semiconductor device, the method including the steps of: (a) providing a silicon wafer structure including a dielectric layer and an underlying layer selected from a semiconductor or electrically conductive material, the dielectric layer being patterned to expose a contact portion of the underlying layer; and (b) depositing by chemical vapour deposition a tungsten layer over the dielectric layer and the contact portion, the deposition being carried out by reaction of a tungsten- containing component and a reducing agent which are introduced into the vicinity of the silicon wafer structure, the deposition step having a first phase in which the process conditions are controlled to form a seed layer of tungsten on the dielectric layer and a second phase in which the process conditions are modified from the first phase to form a blanket tungsten layer over the seed layer which acts as an adhesion layer between the dielectric layer and the blanket tungsten layer. The invention also provides a semiconductor device incorporating a tungsten contact which is disposed in a contact hole of a dielectric layer, the tungsten contact including a seed layer of tungsten which extends over the dielectric layer surface and an overlying layer of blanket tungsten.

Abstract translation: 一种在半导体器件中制造钨触点的方法，所述方法包括以下步骤：（a）提供包括介电层和选自半导体或导电材料的下层的硅晶片结构，所述电介质层被图案化 暴露下层的接触部分; 和（b）通过化学气相沉积在电介质层和接触部分上沉积钨层，沉积通过引入硅晶片结构附近的含钨组分和还原剂的反应进行， 沉积步骤具有第一阶段，其中控制工艺条件以在电介质层上形成钨的种子层，以及第二相，其中工艺条件从第一相修改以在种子层上形成覆盖钨层 其用作介电层和覆盖钨层之间的粘附层。 本发明还提供了一种结合有钨触点的半导体器件，该触点设置在电介质层的接触孔中，该钨触点包括在电介质层表面上延伸的钨晶种层和覆盖层钨层的覆盖层。

公开(公告)号：EP0560598A1

公开(公告)日：1993-09-15

申请号：EP93301833.5

申请日：1993-03-10

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Stansfield, Anthony Ian ,  Barnaby, Catherine Louise ,  Gammack, Richard John ,  Shepherd, Roger Mark

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1063

Abstract: A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each require address translation to identify a physical page in a main memory, a second CAM cell array (52) holding line or word in page addresses which remain the same for virtual and physical addresses, a physical address memory (53) for holding physical page addresses for the main memory corresponding to virtual page addresses in said first array (51), said first array (51) being connected both to said physical address memory (52) to access said physical address memory in response to a hit output from said first CAM cell array and to control circuitry (57) coupled between said first and second arrays (51,52) and the data RAM (50) to access the data RAM (50) in response to hit outputs from both said first and second CAM cell arrays (51,52).

Abstract translation: 用于虚拟寻址的完全关联高速缓冲存储器包括数据RAM（50），用于保持虚拟页面地址的第一CAM单元阵列（51），每个虚拟页面地址都需要地址转换以标识主存储器中的物理页面，第二CAM单元阵列 52）保持对于虚拟和物理地址保持相同的页面地址中的行或字，用于保存对应于所述第一阵列（51）中的虚拟页地址的主存储器的物理页地址的物理地址存储器（53），所述第一 阵列（51）被连接到所述物理地址存储器（52），以响应于来自所述第一CAM单元阵列的命中输出而访问所述物理地址存储器，以及耦合在所述第一和第二阵列之间的控制电路（57） 52）和数据RAM（50），以响应于来自所述第一和第二CAM单元阵列（51,52）的命中输出来访问数据RAM（50）。

公开(公告)号：EP0526029A1

公开(公告)日：1993-02-03

申请号：EP92306412.5

申请日：1992-07-14

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Monk, Trevor Kenneth

IPC: G06F12/02 ,  G11C7/00

CPC classification number: G06F12/0215 ,  G11C7/00

Abstract: A memory is provided with at least one temporary store (21,22) and write abort circuitry (41,42) having a control signal store (41) and gating circuitry (43,44) responsive to an output from the control signal store. Write circuitry loads data and an associated address in the temporary store (21,22) during one write cycle and transfer circuitry (13,23) transfers the data to the associated address during a subsequent write cycle when the write operation is not to be aborted. Read circuitry includes a comparator (27) for comparing a read address with an address in the temporary store (22) and transfer circuitry includes selection circuitry (24) to select an output of data either from the temporary store (21) or the memory (11) dependent on the output of the comparator circuitry (27), an output from the temporary store (21) being prevented if the control signal store (41) indicates that the write operation is to be aborted.

Abstract translation: 存储器具有响应于来自控制信号存储器的输出的至少一个临时存储器（21,22）和写入中止电路（41,42），其具有控制信号存储器（41）和门控电路（43,44）。 写入电路在一个写入周期期间将数据和相关联的地址加载到临时存储器（21,22）中，并且当写入操作不被中止时，传送电路（13,23）在后续写入周期期间将数据传送到相关联的地址 。 读取电路包括用于将读取地址与临时存储器（22）中的地址进行比较的比较器（27），并且传送电路包括从临时存储器（21）或存储器（21）中选择数据输出的选择电路（24） 如果控制信号存储器（41）指示写操作被中止，则根据比较器电路（27）的输出，如果暂存器（21）的输出被阻止，则防止输出。

公开(公告)号：EP0405990A3

公开(公告)日：1993-01-13

申请号：EP90307110.8

申请日：1990-06-28

Applicant: SGS-Thomson Microelectronics Limited

Inventor： May, Michael David ,  Parsons, Brian Jeremy ,  Thompson, Peter William ,  Walker, Christopher Paul Hulme

IPC: H04L12/56

CPC classification number: H04L49/30 ,  G06F15/17375 ,  H04L45/06 ,  H04L45/40 ,  H04L49/101 ,  H04L49/106 ,  H04L49/251 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04Q11/0478

Abstract: A routing switch (1) includes an input (4a) for receiving serial packets from a source node in a computer network, a plurality of outputs (6a...6n) each designating a respective range of destination node identifications, switch circuitry (10) for selectively interconnecting said input to a selected one of said outputs and header reading circuitry (22) for reading the header portion of a packet received at the input prior to receiving all of the packet. The header reading circuitry is coupled to the switch circuitry (10) to connect to said input one of said outputs having a node identification range including the node identification of said header portion. There is also provided a computer network, having a plurality of computer devices and at least one routing switch, and a method of routing messages through such a network.

公开(公告)号：EP0442220A3

公开(公告)日：1992-12-09

申请号：EP90314121.6

申请日：1990-12-21

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Forsyth, Richard Matthew

IPC: G06F1/02

CPC classification number: G06F7/535 ,  G06F1/02 ,  G06F7/60 ,  G06F2207/5352

Abstract: A decoder has a plurality of outputs (R o -R N ) each associated with a particular output value and is arranged to add together two binary numbers (A, B) and to select one of said outputs in dependence on the result of said sum. The decoder comprises a plurality of logic circuits each arranged to receive respective bits of both first and second binary numbers to be added together said logic circuits being arranged to provide, for each output value, a respective result in dependence on the logic states of said bits and on the logic states of respective bits of binary numbers representing the particular output value of the decoder; and logic means for determining when a predetermined condition is satisfied by all the results of the logic circuits associated with an output value of the decoder, whereby that output value is selected. In the preferred embodiment, for adding together two n bit numbers, there are n+l logic circuits (L), each arranged to receive the ith and i-lth bits (Ai, Ai-l, Bi, Bi-l) of first and second n bit numbers, and each arranged to provide an output in dependence on the logic states of said bits and on the logic states of the ith and i-lth bits (Qi, Qi-l) of respective binary numbers which are the ones complement of binary numbers R o ...R N representing each respective output value of the decoder in accordance with the following expression: Ai ⊕ Bi ⊕ Qi ⊕ (Ai-l-Bi-l + Qi-l. (Ai-l + Bi-l)). The predetermined condition is then satisfied when the above expression has a logic value of ONE. A plurality of AND gates are associated respectively with the outputs of the decoder and are each arranged to receive the outputs of the n+l logic circuits for each output value of the decoder. The decoder performs addition and decoding in one step.

公开(公告)号：EP0391561A3

公开(公告)日：1992-01-02

申请号：EP90302868.6

申请日：1990-03-16

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Teague, Martin John ,  Strachan, Andrew Derek ,  Henry, Martin Andrew

IPC: H01L21/82 ,  H01L21/225 ,  H01L21/266

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/31662 ,  H01L21/823892 ,  Y10S148/07

Abstract: A method of forming a well of one conductivity type in a silicon substrate, which method comprises the steps of:-
(a) providing a silicon substrate having a first surface region thereof which is doped with a dopant of one conductivity type and a second surface region thereof which is doped with a dopant of opposite conductivity type, the first and second regions being covered by respective first and second portions of an oxide layer which has been grown on the silicon substrate, the first portion being thicker than the second portion; (b) oxidizing the substrate thereby to increase the thickness of the oxide layer such that the difference in thickness between the first and second portions is reduced; (c) heating the substrate to cause diffusion of the said dopant of one conductivity type thereby to form a well of said one conductivity type in the substrate and also diffusion of the said dopant of opposite conductivity type down into the substrate, the heating step being carried out before, during or after oxidizing step (b); and (d) removing the oxide layer thereby to expose the substrate surface which has a step in the region of the well boundary.

公开(公告)号：EP0442220A2

公开(公告)日：1991-08-21

申请号：EP90314121.6

申请日：1990-12-21

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Forsyth, Richard Matthew

IPC: G06F1/02

CPC classification number: G06F7/535 ,  G06F1/02 ,  G06F7/60 ,  G06F2207/5352

Abstract: A decoder has a plurality of outputs (R o -R N ) each associated with a particular output value and is arranged to add together two binary numbers (A, B) and to select one of said outputs in dependence on the result of said sum. The decoder comprises a plurality of logic circuits each arranged to receive respective bits of both first and second binary numbers to be added together said logic circuits being arranged to provide, for each output value, a respective result in dependence on the logic states of said bits and on the logic states of respective bits of binary numbers representing the particular output value of the decoder; and logic means for determining when a predetermined condition is satisfied by all the results of the logic circuits associated with an output value of the decoder, whereby that output value is selected.
In the preferred embodiment, for adding together two n bit numbers, there are n+l logic circuits (L), each arranged to receive the ith and i-lth bits (Ai, Ai-l, Bi, Bi-l) of first and second n bit numbers, and each arranged to provide an output in dependence on the logic states of said bits and on the logic states of the ith and i-lth bits (Qi, Qi-l) of respective binary numbers which are the ones complement of binary numbers R o ...R N representing each respective output value of the decoder in accordance with the following expression:

Ai ⊕ Bi ⊕ Qi ⊕ (Ai-l-Bi-l + Qi-l. (Ai-l + Bi-l)).


The predetermined condition is then satisfied when the above expression has a logic value of ONE.
A plurality of AND gates are associated respectively with the outputs of the decoder and are each arranged to receive the outputs of the n+l logic circuits for each output value of the decoder.
The decoder performs addition and decoding in one step.

Abstract translation: 解码器具有多个输出（Ro-RN），每个输出与特定输出值相关联，并且被布置为将两个二进制数（A，B）相加，并且根据所述和的结果来选择所述输出之一。 解码器包括多个逻辑电路，每个逻辑电路被布置为接收要相加的第一和第二二进制数的相应位，所述逻辑电路被布置为根据所述位的逻辑状态为每个输出值提供相应的结果 以及表示解码器的特定输出值的二进制数的各个比特的逻辑状态; 以及逻辑装置，用于通过与解码器的输出值相关联的逻辑电路的所有结果来确定何时满足预定条件，由此选择该输出值。 在优选实施例中，为了将两个n位数相加在一起，存在n + 1个逻辑电路（L），每个逻辑电路（L）被布置成接收第一和第i位的第i和第i位（Ai，Ai-1，Bi，Bi-1） 和第二n位数，并且每个被配置为根据所述位的逻辑状态以及作为其的各个二进制数的第i和第i-1位（Qi，Qi-1）的逻辑状态提供输出 Ai（+）Bi（+）Qi（+）（Ai-1-Bi-1 + Qi-1。（） Ai-1 + Bi-1））。 当上述表达式的逻辑值为1时，则满足预定条件。 多个与门分别与解码器的输出相关联，并且各自被布置为接收解码器的每个输出值的n + 1个逻辑电路的输出。 解码器在一个步骤中执行加法和解码。

公开(公告)号：EP0403050A3

公开(公告)日：1991-04-24

申请号：EP90302870.2

申请日：1990-03-16

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Hunt, Paul Anthony ,  Liles, Ian Michael ,  Guite, David Ralph

IPC: H01L21/285

CPC classification number: H01L21/28 ,  H01L21/3105

Abstract: A method of fabricating an electrical contact in a semiconductor device, the method comprising the steps of:-
(a) providing on an underlying silicon substrate (2) a reflowable interlevel dielectric material (14) having a contact opening exposing a contact region of the silicon substrate; (b) heating the silicon substrate and the interlevel dielectric material by a rapid thermal anneal in an oxygen-containing atmosphere thereby to grow an oxide control layer (20) in the contact region and to reflow the dielectric material; (c) depositing a layer of transition metal (28) over the reflowed dielectric material and the control layer; and (d) converting at least part of the transition metal layer into a metallurgic barrier.

公开(公告)号：EP0389142A2

公开(公告)日：1990-09-26

申请号：EP90302343.0

申请日：1990-03-06

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Wise, Adrian Philip ,  Forsyth, Richard Matthew

IPC: G11C7/00 ,  G11C11/41 ,  G11C8/00

CPC classification number: G11C11/419 ,  G11C7/10 ,  G11C7/1018

Abstract: A line delay device comprises a memory having RAM cells in two blocks (14,15), each cell being connected to a pair of bit lines. Memory locations in one block (14) are addressed sequentially and subject to a data transfer while an equate operation is effected on the bit lines of the other block (15). The operations are switched alternately between the two blocks (14,15). In each accessing cycle a plurality of locations are addressed in selected rows of each block (14,15) and the switching between each block is effected without addressing all locations in each row addressed so that the accessing cycle ends in a different block (15) from the starting block (14) and each row used has a plurality of addressed locations.

Abstract translation: 行延迟装置包括具有两个块（14,15）中的RAM单元的存储器，每个单元连接到一对位线。 一个块（14）中的存储器位置被顺序地寻址并经受数据传输，同时在另一个块（15）的位线上进行相等的操作。 操作在两个块（14,15）之间交替切换。 在每个访问周期中，在每个块（14,15）的选定行中寻址多个位置，并且实现每个块之间的切换而不寻址每行寻址的所有位置，使得访问周期以不同的块（15）结束， 来自起始块（14）并且使用的每一行具有多个寻址位置。

公开(公告)号：EP0611014A3

公开(公告)日：1997-10-01

申请号：EP94200820.2

申请日：1990-06-28

Applicant: SGS-Thomson Microelectronics Limited

Inventor： May, Michael David ,  Parsons, Brian Jeremy ,  Thompson, Peter William ,  Walker, Christopher Paul Hulme

IPC: H04L12/56

CPC classification number: H04L49/30 ,  G06F15/17375 ,  H04L45/06 ,  H04L45/40 ,  H04L49/101 ,  H04L49/106 ,  H04L49/251 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04Q11/0478

Abstract: A communications device, particularly but not exclusively for use with a routing circuit is arranged to transmit and receive message packets. It comprises an output buffer (42) which operates to convert data and flow control information into a plurality of bit sequences and to transmit them at a predetermined frequency. An input buffer is operable to decode incoming sequences into data items and flow control information. The input buffer (44) can store the data items and count them and transmit flow control information to the output buffer. A method of encoding the bit sequences as balanced six-bit codes is also described.