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    CTE MATCHED INTERPOSER AND METHOD OF MAKING
    41.
    发明申请
    CTE MATCHED INTERPOSER AND METHOD OF MAKING 审中-公开
    CTE匹配插入器和制造方法

    公开(公告)号：WO2013154497A2

    公开(公告)日：2013-10-17

    申请号：PCT/SE2013/050408

    申请日：2013-04-15

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS, Thorbjörn ,  PERTTU, Daniel

    IPC: H01L23/32 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538

    CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The inventive merit of the present interposer is that it is possible to taylor the coefficient of thermal expansion CTE of the interposer to match components to be attached thereto within very wide ranges. The invention relates to a emiconductor interposer, comprising a substrate (10) of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer- through via (18, 28, 27) comprising metal (27). At least one recess (20)is provided in the first side of the substrate (10) and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure (20). The exposed surfaces of the metal filled via and the metal filled recess (18, 27) are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via (18, 28, 27) comprises a narrow part (18) and a wider part (27), and there are provided contact elements on said routing structure (20) having an aspect ratio, height:diameter,

    Abstract translation: 本发明的插入器的创造性优点是可以在很宽的范围内使插入器的热膨胀系数CTE与匹配的元件相匹配。 本发明涉及一种半导体中介层，包括具有第一侧（FS）和相对的第二侧（BS）的半导体材料的衬底（10）。 存在至少一个包含金属（27）的导电晶片通孔（18,28,27）。 在衬底（10）的第一侧和衬底的半导体材料中提供至少一个凹部（20），该凹部填充有金属并且与提供布线结构（20）的晶片贯通通孔连接。 金属填充通孔和金属填充凹槽（18,27）的暴露表面基本上与衬底的第一侧上的衬底表面齐平。 晶片贯通过孔（18,28,27）包括窄部分（18）和较宽部分（27），并且在所述布线结构（20）上提供纵横比，高度：直径， ; 1：1，优选1：1至2：1。

    CONTROLLING PRESSURE IN CAVITIES ON SUBSTRATES
    45.
    发明申请
    CONTROLLING PRESSURE IN CAVITIES ON SUBSTRATES 审中-公开
    控制基板上的压力

    公开(公告)号：WO2015119564A1

    公开(公告)日：2015-08-13

    申请号：PCT/SE2015/050130

    申请日：2015-02-06

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： WESTIN, Håkan ,  WICKERT, Peter

    IPC: B81C1/00 ,  B81B1/00

    CPC classification number: B81C1/00293

    Abstract: The invention relates to a new method of providing different and controlled atmospheres inside cavities on one and the same chip of a MEMS device. With the new method one can refrain from providing separate getter materials, and thereby the manufacturing is simplified. The method comprises providing a first substrate (20) and a second substrate (28) and making at least one depression (22', 22'') in at least one of the substrates(20). A structural component (26) is provided in or on a surface of at least one of the substrates, said structure containing entrapped, absorbed or adsorbed ions, molecules or atoms of a gas. The substrates are bonded together such that a cavity forms and becomes hermetically sealed. The obtained structure is subjected to conditions so as to release the implanted, absorbed or adsorbed gas atoms, ions or molecules from the substrate to provide said controlled atmosphere inside the cavity.

    Abstract translation: 本发明涉及一种在MEMS器件的同一个芯片上的空腔内提供不同和受控气氛的新方法。 采用这种新方法，可以避免提供单独的吸气剂材料，从而简化制造。 该方法包括提供第一衬底（20）和第二衬底（28），并且在至少一个衬底（20）中形成至少一个凹陷（22'，22“）。 在至少一个基板的表面中或其表面上设置结构部件（26），所述结构包含被截留的，吸收的或吸附的离子，气体的分子或原子。 基板粘合在一起，使得空腔形成并变得密封。 所获得的结构经受条件以从衬底中释放注入的，吸收的或吸附的气体原子，离子或分子，以在空腔内提供所述受控气氛。

    ELECTROLESS METAL THROUGH SILICON VIA
    46.
    发明申请
    ELECTROLESS METAL THROUGH SILICON VIA 审中-公开
    通过硅通孔的化学镀金属

    公开(公告)号：WO2014051511A2

    公开(公告)日：2014-04-03

    申请号：PCT/SE2013051124

    申请日：2013-09-27

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS THORBJOERN ,  KNUTSSON HENRIK

    CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to methods of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface. It comprises providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited Cu on the Ni by a plating process. Line widths and spacings

    Abstract translation: 本发明涉及制造半导体衬底中具有高纵横比的衬底贯穿金属通孔和衬底表面上的金属图案的方法。 它包括提供半导体衬底（晶片）并在衬底上沉积多晶硅。 通过蚀刻掉不需要的部分来图案化衬底表面上的多晶硅。 然后，通过无电处理将Ni选择性地沉积在多晶硅上。 穿过基板形成通孔，其中孔中的壁受到与上述相同的处理。 通过电镀工艺将Cu沉积在Ni上。 晶圆两侧的线宽和间距<10μm。

    INSULATION OF MICRO STRUCTURES
    47.
    发明申请
    INSULATION OF MICRO STRUCTURES 审中-公开
    微结构绝缘

    公开(公告)号：WO2013095260A1

    公开(公告)日：2013-06-27

    申请号：PCT/SE2012/051325

    申请日：2012-11-29

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： KÄLVESTEN, Edvard ,  EBEFORS, Thorbjörn ,  ERIKSSON, Anders

    IPC: H01L21/762 ,  A61M37/00 ,  B81C1/00 ,  H01L21/768

    CPC classification number: A61B5/685 ,  A61B5/04001 ,  A61M37/0015 ,  A61M2037/0053 ,  G01R1/06744 ,  G01R3/00 ,  H01L21/02 ,  H01L21/0226 ,  H01L21/02334 ,  H01L21/02362 ,  H01L21/308 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The application discloses a method of providing a metal coating on a substrate (10), and electrically insulating sections/parts of the metal coated substrate from each other. A substrate is provided with an insulating material in the substrate, said insulating first material extending through the thickness of the substrate and protruding above one surface of the substrate. It forms an enclosed section/portion (14) of the substrate. A protective structure (15) is provided on the insulating material such that it covers the entire circumference thereof. The insulating material is selectively etched to create an under-etch (18) under said protective structure. Finally conductive material (19) is deposited to provide a metal coating over the substrate, whereby the underetch will provide a disruption in the deposited metal coating, thereby electrically insulating the enclosed section from the surrounding substrate.

    Abstract translation: 本申请公开了一种在基板（10）上提供金属涂层并使金属涂覆的基板的部分/部分彼此电绝缘的方法。 衬底在衬底中设置有绝缘材料，所述绝缘第一材料延伸穿过衬底的厚度并突出在衬底的一个表面上方。 它形成衬底的封闭部分/部分（14）。 在绝缘材料上设置保护结构（15），以覆盖其整个周边。 选择性地蚀刻绝缘材料以在所述保护结构下产生下蚀刻（18）。 最后，沉积导电材料（19）以在衬底上提供金属涂层，由此未曝光将在沉积的金属涂层中提供破坏，从而将封闭部分与周围衬底电绝缘。

    A STARTING SUBSTRATE FOR SEMICONDUCTOR ENGINEERING HAVING SUBSTRATE-THROUGH CONNECTIONS AND A METHOD FOR MAKING SAME
    48.
    发明申请
    A STARTING SUBSTRATE FOR SEMICONDUCTOR ENGINEERING HAVING SUBSTRATE-THROUGH CONNECTIONS AND A METHOD FOR MAKING SAME 审中-公开
    具有基板贯通连接的半导体工程的启动基板及其制造方法

    公开(公告)号：WO2012144951A1

    公开(公告)日：2012-10-26

    申请号：PCT/SE2012/050420

    申请日：2012-04-19

    Applicant: SILEX Microsystems AB ,  ERLESAND, Ulf

    Inventor： ERLESAND, Ulf

    IPC: H01L21/768 ,  H01L23/498 ,  H01L27/12 ,  H01L29/78

    CPC classification number: B81B3/0086 ,  B81C1/00222 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to a substrate-through electrical connection (10) for connecting components on opposite sides of a substrate, and a method for making same. The connection comprises a substrate-through via made from substrate material (10). There is a trench (11) provided surrounding said via, the walls of said trench being coated with a layer of insulating material (12) and the trench (11) is filled with conductive or semi-conductive material (13). A doping region (15) for threshold voltage adjustment is provided in the via material in the surface of the inner trench wall between insulating material (12) and the material (10) in the via. There are contacts (17, 17) to the via on opposite sides of the substrate, and a contact (18) to the conductive material (13) in the trench (11) so as to enable the application of a voltage to the conductive material (13).

    Abstract translation: 本发明涉及一种用于连接衬底相对两侧的部件的基底通电连接件（10）及其制造方法。 该连接包括由基底材料（10）制成的基底通孔。 设置有围绕所述通孔的沟槽（11），所述沟槽的壁涂覆有绝缘材料层（12），并且沟槽（11）填充有导电或半导体材料（13）。 用于阈值电压调整的掺杂区域（15）设置在通孔材料中，在通孔中的绝缘材料（12）和材料（10）之间的内沟槽壁的表面中。 在衬底的相对侧上有通孔的触点（17,17）和与沟槽（11）中的导电材料（13）的触点（18），以便能够向导电材料施加电压 （13）。

    NOVEL BONDING PROCESS AND BONDED STRUCTURES
    49.
    发明申请
    NOVEL BONDING PROCESS AND BONDED STRUCTURES 审中-公开

    公开(公告)号：WO2010126448A3

    公开(公告)日：2010-11-04

    申请号：PCT/SE2010/050479

    申请日：2010-04-30

    Applicant: SILEX MICROSYSTEMS AB ,  EBEFORS, Thorbjörn ,  KÄLVESTEN, Edward ,  SVEDIN, Niklas ,  ERIKSSON, Anders

    Inventor： EBEFORS, Thorbjörn ,  KÄLVESTEN, Edward ,  SVEDIN, Niklas ,  ERIKSSON, Anders

    IPC: H01L23/10 ,  B81B7/00

    Abstract: The invention relates to a sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in said strips is a material bonding said semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. The invention also provides a monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device comprising a first substrate and a second substrate, bonded together with a sealing and bonding structure according to the invention. A method comprises providing a sealing and bonding material structure according to the invention on at least one of two wafers and applying a force and optionally heat to the wafers to join them.

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