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公开(公告)号：JP2004007692A
公开(公告)日：2004-01-08
申请号：JP2003145156
申请日：2003-05-22
Applicant: ST MICROELECTRONICS INC
Inventor： MAKAROV ALEKSEJ
IPC: H04L27/22 , H04B7/01 , H04B7/26 , H04L27/00 , H04L27/227 , H04L27/233
Abstract: PROBLEM TO BE SOLVED: To provide an arithmetically efficient system and method to measure a frequency offset error. SOLUTION: This invention detects and stores counter-clockwise and clockwise quadrant transitions with respect to a composite signal received for a time period, then compares the transitions with each other to obtain information denoting both the magnitude and the phase of a frequency offset error, and further detects and stores zero crossing of the composite signal received for the same time period. The stored crossing provides information denoting the magnitude of the frequency offset. Then using the decided magnitude and phase of the frequency offset error adjusts the frequency of a local oscillator to provide enhanced receiver performance. COPYRIGHT: (C)2004,JPO
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42.发明专利
公开(公告)号：JP2003258751A
公开(公告)日：2003-09-12
申请号：JP2002368096
申请日：2002-12-19
Applicant: ST MICROELECTRONICS INC
Inventor： WANG XIANBIN
Abstract: PROBLEM TO BE SOLVED: To provide technology for improving the performance of DSL modems. SOLUTION: A DSL duplexing ratio for a new communication is selected according to the communications needs of an application. Namely, a required upstream and downstream bit rate for application communications is determined. From the ratio of these bit rates, a desired duplexing ratio is calculated. Next, the operation of the modem is adapted to choose a duplexing ratio that approximates the desired duplexing ratio for the application. To optimize modem operation, the size and position of the upstream and downstream bandwidths used for transmission are selected when the bit rate necessary for making the transmission is less than the total available bandwidth provided by the chosen duplexing ratio. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JP2003249074A
公开(公告)日：2003-09-05
申请号：JP2003023822
申请日：2003-01-31
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C
Abstract: PROBLEM TO BE SOLVED: To provide an improved circuit and a method for testing deterioration of a ferroelectric memory cell. SOLUTION: A circuit and a method for testing a memory cell of a ferroelectric memory device equipped with an array consisting of ferroelectric memory is provided. The test circuit is coupled to the bit lines, the determines selectively the voltage levels appearing on the bit lines based on a measured current level and supplies externally an electrical signal representative of the sensed voltage levels to the ferroelectric memory device. In this way, ferroelectric memory cells exhibiting degraded performance is identified. COPYRIGHT: (C)2003,JPO
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44.发明专利
公开(公告)号：JP2003234372A
公开(公告)日：2003-08-22
申请号：JP2003023178
申请日：2003-01-31
Applicant: ST MICROELECTRONICS INC
Inventor： HARRY MICHAEL SIEGEL , ANTHONY M CHU
IPC: H01L21/60 , H01L21/52 , H01L21/58 , H01L23/544
Abstract: PROBLEM TO BE SOLVED: To provide an improved system and a method in which an integrated circuit die is matched with an integrated circuit board. SOLUTION: The integrated circuit die is made to match with the integrated circuit board for disposing an adherent made of a plurality of deformable substances on the board of a position to match the die. A marking unit is indexed with respect to a first positioning hole and a second positioning hole in the board. An adherent made of the deformable substances with a tolerance of less than 100 microns with respect to the first and second positioning holes is marked by the marking unit. The marked part of the adherent is formed with a pocket for receiving the integrated circuit die. This enables the precise matching of the die on the board in three dimensions. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JP2003199034A
公开(公告)日：2003-07-11
申请号：JP2002308192
申请日：2002-10-23
Applicant: ST MICROELECTRONICS INC
Inventor： COLAVIN OSVALDO M , LUSINCHI EMMANUEL
IPC: G06T3/40 , H04N1/00 , H04N5/262 , H04N5/77 , H04N5/781 , H04N5/907 , H04N5/91 , H04N5/92 , H04N5/93 , H04N101/00
Abstract: PROBLEM TO BE SOLVED: To improve the image processing in a digital camera. SOLUTION: A method is provided for storing a plurality of still images for forming a panorama image, as follows. A first image forming a part of a series of images for forming the panorama image is received and stored in a memory. When one or more images following the first image are received, one or more panorama parameters between the present image and the previous image stored in the memory are calculated, and the present image is stored in the memory, together with the one or more panorama parameters. COPYRIGHT: (C)2003,JPO
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Patent Agency Ranking
公开(公告)号：JP2003175018A
公开(公告)日：2003-06-24
申请号：JP2002223040
申请日：2002-07-31
Applicant: ST MICROELECTRONICS INC
Inventor： SABATINI MARCO
Abstract: PROBLEM TO BE SOLVED: To provide a power management technique for realizing recovery from an electrostatic discharge latchup event for a fingerprint sensor system. SOLUTION: A power management unit monitors current drawn by a fingerprint sensor circuit and generates a 'heartbeat' signal during normal operation. When the latchup event occurs, with attendant increase in current drawn by the fingerprint sensor circuitry, the heartbeat signal terminates and an interrupt is subsequently triggered to start a latchup recovery routine. Power to the fingerprint sensor circuitry is switched off and the interrupt is then cleared by writing appropriate values to control bits within the power management register. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JP2003164193A
公开(公告)日：2003-06-06
申请号：JP2002302024
申请日：2002-10-16
Applicant: ST MICROELECTRONICS INC
Inventor： PEDRAZZINI GIORGIO , FONG HIN SING , RAVISHANKER KRISHNAMOORTHY
Abstract: PROBLEM TO BE SOLVED: To provide a multi-mode motor controller architecture whose form is easily repetitively changeable so as to be operated in a plurality of operation modes, and which is allowed to be operated relating to a wide-range controller circuit. SOLUTION: The multi-mode motor controller architecture has a motor, an integrated circuit controller, and an integrated-circuit driver circuit. The integrated circuit controller has a pulse generator, DAC, ADC, and a digital compensator circuit. The integrated-circuit-driver circuit is in a communicating state with the controller; and has an error amplifier, a first and second output amplifier to drive the motor, and a sense amplifier. The motor controller architecture is configurable so as to be operated in a linear mode, a pulse mode, or a switchable linear/pulse mode. The controller architecture is, for example, allowed to be obtained with an external compensation circuit of a resistor/ capacitor circuit or the like, or with a digital compensation circuit positioned within the controller integrated circuit. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JP2003123490A
公开(公告)日：2003-04-25
申请号：JP2002224663
申请日：2002-08-01
Applicant: ST MICROELECTRONICS INC
Inventor： FASOLI LUCA GIOVANNI
Abstract: PROBLEM TO BE SOLVED: To provide a user configurable dual bank memory device. SOLUTION: The memory device has a plurality of core banks consisting of memory cells and a set of storage elements having stored therein configuration information. The configuration information may be used to configure, that is, to group core banks of memory cells to form a dual bank memory device. The memory device has a control circuit for preventing a memory read operation from being completed in a core bank or user-configured dual bank in which an ongoing memory modify (program or erase) operation is being performed. The memory device further has a first set of sense amplifiers dedicated to performing sense amplification only during memory read operations, and a second sense amplifiers dedicated to performing sense amplification only during memory modify operations.
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49.发明专利
公开(公告)号：JP2003085903A
公开(公告)日：2003-03-20
申请号：JP2002205934
申请日：2002-07-15
Applicant: ST MICROELECTRONICS INC
Inventor： STEVENS ARTHUR L , DELELLIS JOSEPH R
Abstract: PROBLEM TO BE SOLVED: To provide an improved method and device which discriminate and control the position of a read/write head relatively to a track on a magnetic disk. SOLUTION: A head position control system for the dual-stage actuation is provided. A feedback system is provided which correct a primary and a secondary input command to generate a primary and a secondary error signal. A controller receives the primary and secondary error signals and sends positioning information to a primary and a secondary actuator. The feedback system generates a position error signal (PES) by using information from a servo wedge and line-out information and the secondary error signal by using PES, and also generates a regenerated error signal for a primary actuator arm by processing a counterelectromotive force signal from the primary actuator. The primary error signal is generated by correcting the primary input signal with the regenerated error signal.
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公开(公告)号：JP2002260399A
公开(公告)日：2002-09-13
申请号：JP2001395615
申请日：2001-12-27
Applicant: ST MICROELECTRONICS INC
Inventor： LAURENT DUANE GILES
IPC: G01R31/28 , G01R31/319 , G11C7/06 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C29/12 , G11C29/00
Abstract: PROBLEM TO BE SOLVED: To provide a memory device which can decide sensitivity of a sense amplifier. SOLUTION: This dynamic random access memory(DRAM) has a pair of bit lines provided with first bit lines and second bit lines. Memory cells and sense amplifiers are coupled to the bit lines. First characterization cells are coupled between the first bit lines and a first reference supply line. The first characterization cell has a capacitor. In the same way, Second characterization cells are coupled between the first bit lines and a first reference supply line. The second characterization cell also has a capacitor, but preferably, has a different capacitor. In an appropriate embodiment, a same characterization cell is coupled to the second bit lines.
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