公开(公告)号：KR1020110075312A

公开(公告)日：2011-07-06

申请号：KR1020090131729

申请日：2009-12-28

Applicant: 삼성전자주식회사

Inventor： 김민석 ,  박기태

IPC: G11C16/10 ,  G11C16/12

CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C16/0416 ,  G11C16/0483 ,  G11C2211/5621

Abstract: PURPOSE: A flash memory device and a program method thereof are provided to improve program speed by removing a program verification operation of a small memory cell which has a little threshold voltage change. CONSTITUTION: In a flash memory device and a program method thereof, a program of 1 -th bit of a 4- bit MLC is performed. The program of an upper 3 bit excluding a least significant bit(LSB) is performed through a plurality of program steps. Each program step is composed of a plurality of program loops. The level of change of a threshold voltage is highest at sT7 and lowest at ST4. A program verification operation of ST5 and ST6 program is removed. The program verification operation of ST7 program is performed. The program verification operation of ST4 program is performed.

Abstract translation: 目的：提供一种闪存器件及其编程方法，通过去除具有小阈值电压变化的小存储器单元的程序验证操作来提高程序速度。 构成：在闪速存储器件及其编程方法中，执行4位MLC的第1位的程序。 通过多个程序步骤执行不包括最低有效位（LSB）的高3位的程序。 每个程序步骤由多个程序循环组成。 阈值电压的变化水平在sT7为最高，在ST4为最低。 删除ST5和ST6程序的程序验证操作。 执行ST7程序的程序验证操作。 执行ST4程序的程序验证操作。

公开(公告)号：KR1020110059313A

公开(公告)日：2011-06-02

申请号：KR1020090116010

申请日：2009-11-27

Applicant: 삼성전자주식회사

Inventor： 박민건 ,  박기태

IPC: G11C16/34 ,  G11C16/14

CPC classification number: G06F12/0246 ,  G06F2212/7211 ,  G11C7/04 ,  G11C13/0035 ,  G11C16/26 ,  G11C16/349 ,  G11C16/34 ,  G11C16/14

Abstract: PURPOSE: A nonvolatile memory device, a memory management system having the same, and a wear leveling method thereof are provided to improve the performance and lifespan of a non-volatile memory device by managing wear quality according to the number of erasures and degree of wear. CONSTITUTION: In a nonvolatile memory device, a memory management system having the same, and a wear leveling method thereof, a memory controller comprises a threshold voltage measure controller(120 1). The threshold voltage measure controller measures the threshold voltage of a charge loss measurement cell. The threshold voltage measure controller calculates the degree of change of the threshold voltage. The threshold voltage measure controller calculates a valid erasure frequency. The memory cell array comprises a valid erasure frequency table(120 2). The valid erasure frequency table comprises an erasure frequency table. The erasure frequency table stores the erasure frequencies of a plurality of memory blocks.

Abstract translation: 目的：提供一种非易失性存储器件，具有其的存储器管理系统及其磨损均衡方法，以通过根据擦除次数和磨损程度管理磨损品质来改善非易失性存储器件的性能和寿命 。 构成：在非易失性存储器件中，具有相同的存储器管理系统及其磨损均衡方法，存储器控制器包括阈值电压测量控制器（120 1）。 阈值电压测量控制器测量电荷损失测量单元的阈值电压。 阈值电压测量控制器计算阈值电压的变化程度。 阈值电压测量控制器计算有效的擦除频率。 存储单元阵列包括有效擦除频率表（120 2）。 有效擦除频率表包括擦除频率表。 擦除频率表存储多个存储块的擦除频率。

公开(公告)号：KR1020110037100A

公开(公告)日：2011-04-13

申请号：KR1020090094376

申请日：2009-10-05

Applicant: 삼성전자주식회사

Inventor： 김보근 ,  박기태

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C11/5628 ,  G11C7/1048 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454 ,  G11C2211/5621

Abstract: PURPOSE: A non-volatile memory device and a program method thereof are provided to reduce power consumption in programming by making threshold voltage distribution narrow. CONSTITUTION: In a non-volatile memory device and a program method thereof, a page buffer(130) is connected to the bit line of a memory cell. A control logic(140) controls the page buffer. The pre charge of the bit line is deactivated in a program verification operation before a specific loop count. The precharge of the bit line is activated in the program verification operation at a specific loop count and after then. A loop count value is stored in the page buffer.

Abstract translation: 目的：提供非易失性存储器件及其编程方法，以通过使阈值电压分布窄而减少编程中的功耗。 构成：在非易失性存储器件及其编程方法中，页缓冲器（130）连接到存储器单元的位线。 控制逻辑（140）控制页面缓冲器。 在特定循环计数之前的程序验证操作中，位线的预充电被禁用。 在程序验证操作中，以特定的循环次数激活位线的预充电。 循环计数值存储在页面缓冲区中。

公开(公告)号：KR1020100107174A

公开(公告)日：2010-10-05

申请号：KR1020090025330

申请日：2009-03-25

Applicant: 삼성전자주식회사

Inventor： 박기태 ,  강명곤

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/349 ,  G11C16/10 ,  G11C16/3495

Abstract: PURPOSE: A non-volatile memory device and a programming method thereof are provided to increase the lifecycle of the non-volatile memory device by uniformly distributing a deletion or program period for the memory block over the overall area of the non-volatile memory. CONSTITUTION: A memory cell array(110) comprises memory cells arranged in a plurality of rows and columns. A write and read circuit(130) operates as a detection amplifier or a write driver according to an operation mode. The deletion/program period data read from the write and read circuit is offered as control logic.

Abstract translation: 目的：提供非易失性存储器件及其编程方法，以通过在非易失性存储器的整个区域上统一分配存储器块的删除或编程周期来增加非易失性存储器件的生命周期。 构成：存储单元阵列（110）包括以多行和列排列的存储单元。 写和读电路（130）根据操作模式操作为检测放大器或写驱动器。 从写入和读取电路读取的删除/编程周期数据作为控制逻辑提供。

公开(公告)号：KR1020100064481A

公开(公告)日：2010-06-15

申请号：KR1020080122927

申请日：2008-12-05

Applicant: 삼성전자주식회사

Inventor： 박기태 ,  정영욱

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3418 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

Abstract: PURPOSE: A memory device and a method for driving the same are provided to prevent the disturbance of a program by boosting a cell which is prohibited to be programmed with high power. CONSTITUTION: A semiconductor system(200) includes a memory device and a processor(220). The processor controls the writing operation, the reading operation or the verifying-reading operation of the semiconductor device. A timing controller performs the verifying-reading operation or a program operation in response with control signal from the processor. A battery(250) supplies operational power to the memory device and the processor. An input-output device provides interface with an external data process device for transmitting and receiving data.

Abstract translation: 目的：提供一种存储装置及其驱动方法，以通过增强禁止以高功率编程的单元来防止程序的干扰。 构成：半导体系统（200）包括存储器件和处理器（220）。 处理器控制半导体器件的写入操作，读取操作或验证读取操作。 定时控制器响应于来自处理器的控制信号执行验证读取操作或程序操作。 电池（250）向存储器件和处理器提供操作电力。 输入输出设备提供与用于发送和接收数据的外部数据处理设备的接口。

公开(公告)号：KR1020100058166A

公开(公告)日：2010-06-03

申请号：KR1020080116886

申请日：2008-11-24

Applicant: 삼성전자주식회사

Inventor： 황순욱 ,  박기태 ,  이재욱 ,  주한성

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/06

CPC classification number: G11C16/3404 ,  G11C16/344

Abstract: PURPOSE: A nonvolatile memory device and a memory system thereof are provided to supply a post program for improving a pass voltage window by controlling a develop time when a precharge voltage is discharged. CONSTITUTION: In a nonvolatile memory device and a memory system thereof, a memory cell array(110) is composed of a plurality of memory blocks. A decoder(130) is connected to a plurality of memory blocks through a word line. A page buffer circuit(120) is connected to a plurality of memory blocks through the bit line. The control logic controls a voltage supplied to the word line and the bit line according to the location of a memory block. A control logic(150) controls the develop time when a precharge voltage applied to the bit line is discharged.

Abstract translation: 目的：提供非易失性存储器件及其存储器系统，以通过控制放电时的显影时间来提供用于改善通过电压窗口的后期程序。 构成：在非易失性存储器件及其存储器系统中，存储单元阵列（110）由多个存储块构成。 解码器（130）通过字线连接到多个存储器块。 页面缓冲电路（120）通过位线连接到多个存储器块。 控制逻辑根据存储块的位置来控制提供给字线和位线的电压。 当施加到位线的预充电电压被放电时，控制逻辑（150）控制显影时间。

公开(公告)号：KR1020100043484A

公开(公告)日：2010-04-29

申请号：KR1020080102536

申请日：2008-10-20

Applicant: 삼성전자주식회사

Inventor： 강명곤 ,  박기태

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524

Abstract: PURPOSE: A flash memory device is provided to reduce manufacturing costs and improve the integration rate of a memory device by using a dummy transistor in order to select a memory cell string which is structured to a common bit line. CONSTITUTION: A first memory cell string is connected to a bit line(BL) through a first and a second dummy transistor. A second memory cell string is connected to the bit line through a third and fourth dummy transistor. The first and the third dummy transistor are connected to a first dummy word line(DWL1). The second and the fourth dummy transistor are connected to a second dummy word line(DWL2). The threshold voltage of the first and the third dummy transistor is set to be different from each other. The threshold voltage of the second and the fourth dummy transistor is set to be different from each other.

Abstract translation: 目的：提供闪速存储器件，以通过使用虚拟晶体管来降低制造成本并提高存储器件的积分率，以选择构成公共位线的存储单元串。 构成：第一存储单元串通过第一和第二虚拟晶体管连接到位线（BL）。 第二存储单元串通过第三和第四虚拟晶体管连接到位线。 第一和第三虚拟晶体管连接到第一虚拟字线（DWL1）。 第二和第四虚拟晶体管连接到第二虚拟字线（DWL2）。 第一和第三虚拟晶体管的阈值电压被设定为彼此不同。 第二和第四虚拟晶体管的阈值电压被设定为彼此不同。

公开(公告)号：KR1020100021246A

公开(公告)日：2010-02-24

申请号：KR1020080080059

申请日：2008-08-14

Applicant: 삼성전자주식회사

Inventor： 박기태 ,  강명곤

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C5/063 ,  G11C11/5642

Abstract: PURPOSE: A memory apparatus protecting a read disturbance and a method thereof are provided to prevent a bit error generating from the reading disturbance by applying a preset voltage to a common source line in a control logic. CONSTITUTION: A first cell string is connected between a first bit line and a first common source line. A second cell string is connected between a second bit line which is adjacent to the first bit line and a second common source line. A control logic(117) independently controls the first and second common source lines. The control logic applies a preset voltage to the second common source line. The first cell string comprises a cell string of even number. A second cell string comprises a cell string of odd number.

Abstract translation: 目的：提供保护读取干扰的存储装置及其方法，以通过向控制逻辑中的公共源线施加预设电压来防止由读取干扰产生的位错误。 构成：第一单元串连接在第一位线和第一公共源极线之间。 第二单元串连接在与第一位线相邻的第二位线和第二公共源极线之间。 控制逻辑（117）独立地控制第一和第二公共源极线。 控制逻辑将预设电压施加到第二公共源极线。 第一单元串包括偶数的单元串。 第二单元串包括奇数的单元串。

公开(公告)号：KR1020100013187A

公开(公告)日：2010-02-09

申请号：KR1020080074746

申请日：2008-07-30

Applicant: 삼성전자주식회사

Inventor： 박기태

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C5/147 ,  G11C8/12 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2013/0083

Abstract: PURPOSE: A non-volatile memory device for extracting parameters and a nonvolatile memory system including the same are provided to set properly optimized parameters by measuring a reference parameter for each plane, block and page. CONSTITUTION: A memory cell array(111) comprises a plurality of memory blocks. A control logic stores a parameter for accessing each memory block. A control logic(117) detects the change of a parameter while accessing each memory block. The control logic stores the changed parameter to a memory cell array according to the detection result. The control logic accesses at least one memory block among a plurality of memory blocks. The control logic uses the parameter saved in the memory cell array.

Abstract translation: 目的：提供用于提取参数的非易失性存储器件和包括其的非易失性存储器系统，以通过测量每个平面，块和页面的参考参数来设置适当优化的参数。 构成：存储单元阵列（111）包括多个存储块。 控制逻辑存储用于访问每个存储器块的参数。 控制逻辑（117）在访问每个存储器块时检测参数的变化。 控制逻辑根据检测结果将改变的参数存储到存储单元阵列。 控制逻辑访问多个存储器块中的至少一个存储器块。 控制逻辑使用保存在存储单元阵列中的参数。

公开(公告)号：KR1020090127023A

公开(公告)日：2009-12-09

申请号：KR1020080101465

申请日：2008-10-16

Applicant: 삼성전자주식회사

Inventor： 강용훈 ,  박기태

IPC: H01L27/105 ,  H01L21/28

CPC classification number: G11C7/18 ,  G11C8/14 ,  H01L27/11529 ,  H01L27/1157

Abstract: PURPOSE: A multi-layered memory device and an operation method thereof are provided to improve operation performance of the memory device, by enabling at least one memory cell array to perform read/write operation at the same time. CONSTITUTION: A first semiconductor substrate(10) has a memory cell array comprising a number of memory cells. A second semiconductor substrate(20) is stacked on the first semiconductor substrate, and has a bit line and a page buffer connected to the bit line in correspondence to the memory cell array. A bit line contact is formed between the first semiconductor substrate and the second semiconductor substrate. The bit line contact connects the page buffer and memory cell array.

Abstract translation: 目的：通过使至少一个存储单元阵列同时执行读/写操作，提供了一种多层存储器件及其操作方法，以提高存储器件的操作性能。 构成：第一半导体衬底（10）具有包括多个存储单元的存储单元阵列。 第二半导体衬底（20）堆叠在第一半导体衬底上，并且对应于存储单元阵列具有连接到位线的位线和页缓冲器。 在第一半导体衬底和第二半导体衬底之间形成位线接触。 位线触点连接页面缓冲区和存储单元阵列。