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公开(公告)号：KR101519061B1
公开(公告)日：2015-05-11
申请号：KR1020080006236
申请日：2008-01-21
Applicant: 삼성전자주식회사
Abstract: 본 발명은 하나의 고전압 레벨 쉬프터를 공유하는 로우 디코더를 갖는 플래쉬 메모리 장치에 대하여 개시된다. 플래쉬 메모리 장치는 적어도 2개 이상의 메모리 셀 어레이 블락들을 포함한다. 메모리 셀 어레이 블락들은, 복수개의 워드라인들과 복수개의 비트라인들을 포함하고, 하나의 비트라인에 직렬 연결된 복수개의 메모리 셀들이 하나의 스트링을 구성하고, 하나의 워드라인에 연결되는 메모리 셀들을 기준으로 페이지로 구분되고, 복수개의 페이지들로 구성된 블락으로 구분된다. 적어도 2개의 메모리 셀 어레이 블락들이 하나의 로우 디코더를 공유한다. 로우 디코더는, 제1 메모리 셀 어레이 블락을 선택하는 제1 블락 신호와 제2 메모리 셀 어레이 블락을 선택하는 제2 블락 신호에 응답하여 블락 선택 신호를 발생하는 블락 디코더, 블락 선택 신호에 응답하여 고전압의 블락 워드라인 신호를 발생하는 고전압 레벨 쉬프터, 그리고 블락 워드라인 신호에 응답하여 제1 메모리 셀 어레이 블락의 워드라인들로 제1 구동 전압들을 전달하는 제1 패스 트랜지스터부와 제2 메모리 셀 어레이 블락의 워드라인들로 제2 구동 전압들을 전달하는 제2 패스 트랜지스터부를 포함한다.
플래쉬 메모리 장치, 메모리 셀 어레이 블락, 메모리 셀 어레이 레이어, 로 우 디코더, 칩 레이아웃 면적, 프로그램 디스터브 현상Abstract translation: 本发明涉及具有共享一个高电压电平移位器的行解码器的闪存器件。 闪存器件包括至少两个存储单元阵列块。 存储单元阵列块，包括多条字线和多条位线，多条串联连接到构成该串中的一个所述位线中的一个存储器单元，和基准存储单元连接到一条字线 并分成由多个页面构成的块。 至少两个存储器单元阵列块共享一个行解码器。 行解码器，所述第一存储器单元阵列，用于选择块和到块信号的第二响应，用于响应选择所述存储单元阵列块的块解码器，用于产生块选择信号的高电压的块选择信号的第一块信号 块的高电压电平转换器，用于产生字线信号，并且响应于所述信号的第一存储单元，第一传输晶体管部分和第二存储单元阵列块携带第一驱动电压施加到阵列块的字线块字线， 以及第二传输晶体管，用于将第二驱动电压传输到字线。
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公开(公告)号：KR1020100023280A
公开(公告)日：2010-03-04
申请号：KR1020080081960
申请日：2008-08-21
Applicant: 삼성전자주식회사
CPC classification number: G11C16/0483 , G11C16/10
Abstract: PURPOSE: A flash memory device and a memory system including the same are provided to improve the operation speed of the flash memory device by programming all cell strings at the same time with the application of a bias voltage. CONSTITUTION: A first switch(111_1) connects electrically one of a first and a second cell strings to a first bit-line. A second switch(113_1) connects electrically to the second cell string to a second bit-line. A control logic(150) applies a bias voltage to the first cell string through the first bit-line. The control logic applies the bias voltage to the second cell string through the second bit-line. The control logic controls the first and the second cell strings to be programmed simultaneously.
Abstract translation: 目的：提供闪速存储器件和包括其的存储器系统，以通过施加偏置电压同时编程所有单元串来提高闪存器件的操作速度。 构成：第一开关（111_1）将第一和第二单元串之一电连接到第一位线。 第二开关（113_1）电连接到第二单元串到第二位线。 控制逻辑（150）通过第一位线将偏置电压施加到第一单元串。 控制逻辑通过第二位线将偏置电压施加到第二单元串。 控制逻辑控制要同时编程的第一和第二单元串。
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公开(公告)号：KR1020090080337A
公开(公告)日：2009-07-24
申请号：KR1020080006236
申请日：2008-01-21
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3418 , G11C7/02 , G11C8/10 , G11C16/0483 , G11C16/3427 , G11C17/16 , G11C29/52 , G11C16/08 , G11C5/02 , G11C5/063 , G11C16/30
Abstract: A flash memory device is provided to reduce a chip layout area by sharing one row decoder between two memory cell array blocks. Each of first and second memory cell array blocks includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. A row decoder(311) includes a block decoder(410), a high voltage level shifter(420), a first pass transistor(441) and a second pass transistor(442). The block decoder generates the block selection signal in response to a first block signal and a second block signal. The high voltage level shifter generates the block word line signal of the high voltage in response to the block selection signal. The first pass transistor transmits the first driving voltage to the word line of the first memory cell array block in response to the block word line signal. The second pass transistor transmits the second driving voltage to the word line of the second memory cell array block in response to the block word line signal.
Abstract translation: 提供闪速存储器件以通过在两个存储单元阵列块之间共享一行解码器来减小芯片布局区域。 第一和第二存储单元阵列块中的每一个包括多个字线，多个位线和多个存储器单元。 行解码器（311）包括块解码器（410），高电压电平移位器（420），第一传输晶体管（441）和第二传输晶体管（442）。 块解码器响应于第一块信号和第二块信号而产生块选择信号。 高电平电平移位器响应于块选择信号产生高电压的块字线信号。 第一通过晶体管响应于块字线信号将第一驱动电压传输到第一存储单元阵列块的字线。 第二传输晶体管响应于块字线信号将第二驱动电压传输到第二存储单元阵列块的字线。
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公开(公告)号：KR1020080114251A
公开(公告)日：2008-12-31
申请号：KR1020070063621
申请日：2007-06-27
Applicant: 삼성전자주식회사
CPC classification number: G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/30
Abstract: A non volatile memory device is provided to reduce layout area by reducing an unnecessary switching transistor. A non volatile memory device comprises a memory cell array, a first type global word line decoder, and a second type global word line decoder. The memory cell array includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells comprising in order to read out data through a plurality of bit lines. The first and second type global word lines selectively provides a voltage of a different level of 3 kinds with a word line corresponding among a plurality of word lines.
Abstract translation: 提供非易失性存储器件以通过减少不必要的开关晶体管来减少布局面积。 非易失性存储器件包括存储单元阵列，第一类型全局字线解码器和第二类型全局字线解码器。 存储单元阵列包括多个字线，多个位线和多个存储器单元，其包括用于通过多个位线读出数据。 第一和第二类型全局字线选择性地将三种不同电平的电压与多条字线之间对应的字线提供。
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公开(公告)号：KR100819552B1
公开(公告)日：2008-04-07
申请号：KR1020060105838
申请日：2006-10-30
Applicant: 삼성전자주식회사
IPC: G11C5/14
CPC classification number: G11C11/4091 , G11C11/4094 , G11C2211/4016
Abstract: A semiconductor memory device and an operation method of the same are provided to read data without a reference memory cell, as simplifying configuration of a sensing block used for reading data. A memory cell array(100) comprises a first block comprising a first memory cell and a second block comprising a second memory cell. The first memory cell is connected between a first bit line and a source line receiving a source voltage, and has a floating body having a gate connected to a first word line. The second memory cell is connected between a second bit line and the source line, and has a floating body having a gate connected to a second word line. A bit line isolation part transmits data between the first bit line and a sense bit line, and transmits data between the second bit line and an inverted sense bit line. A sense amplifier part equalizes the sense bit line and the inverted sense bit line with an equalization voltage level during equalization operation, and precharges one of the sense bit line and the inverted sense bit line with a first precharge voltage line higher than the equalization voltage and the other one of the sense bit line and the inverted sense bit line with a second precharge voltage level lower than the first precharge voltage during precharge operation, and senses and amplifies voltage difference between the sense bit line and the inverted sense bit line during read and write operation.
Abstract translation: 提供半导体存储器件及其操作方法，用于读取没有参考存储单元的数据，作为用于读取数据的感测块的简化配置。 存储单元阵列（100）包括包括第一存储单元的第一块和包括第二存储单元的第二块。 第一存储单元连接在第一位线和接收源电压的源极线之间，并且具有连接到第一字线的栅极的浮体。 第二存储单元连接在第二位线和源极线之间，并且具有连接到第二字线的栅极的浮体。 位线隔离部分在第一位线和感测位线之间传输数据，并且在第二位线和反相感测位线之间发送数据。 感测放大器部件在均衡操作期间具有均衡电压电平来均衡感测位线和反相感测位线，并且利用高于均衡电压的第一预充电电压线对感测位线和反相检测位线中的一个进行预充电，以及 在预充电操作期间具有比第一预充电电压低的第二预充电电压电平的感测位线和反相感测位线中的另一个，并且在读取期间感测和放大感测位线和反相检测位线之间的电压差，并且 写操作。
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Patent Agency Ranking
公开(公告)号：KR1020100123140A
公开(公告)日：2010-11-24
申请号：KR1020090042188
申请日：2009-05-14
Applicant: 삼성전자주식회사
IPC: G11C7/10
CPC classification number: G11C16/10 , G11C5/025 , G11C16/26 , G11C2207/105
Abstract: PURPOSE: A stacked flash memory device using TSV is provided to prevent the change of device characteristics while reducing current consumption. CONSTITUTION: A flash memory device(100) comprises a plurality of the chips(CHP1,CHP2,CHP3) and TSV(Through Silicon Via). A plurality of chips are stacked. TSV transmit an address or data to chips and receives them from the chips. Each chip has an input/output pad, a TSV pad, and a controller. The input/output pad receives the address or data from the outside and transmits them to the outside. The TSV pad receives the address or data from the TSV and transmits them to the TSV. The controller control the activation of the input/output pad and the TSV pad.
Abstract translation: 目的：提供使用TSV的堆叠闪存器件，以防止器件特性的变化，同时降低电流消耗。 构成：闪存器件（100）包括多个芯片（CHP1，CHP2，CHP3）和TSV（通过硅通孔）。 堆叠多个芯片。 TSV将地址或数据发送到芯片，并从芯片接收它们。 每个芯片都有一个输入/输出焊盘，一个TSV焊盘和一个控制器。 输入/输出板从外部接收地址或数据，并将它们发送到外部。 TSV焊盘从TSV接收地址或数据，并将其发送到TSV。 控制器控制输入/输出焊盘和TSV焊盘的激活。
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公开(公告)号：KR1020100064496A
公开(公告)日：2010-06-15
申请号：KR1020080122958
申请日：2008-12-05
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/24 , G11C16/30
Abstract: PURPOSE: A memory device which reduces a coupling phenomenon between memory cells and a semiconductor system including the same are provided to constantly maintain the channel voltage of a cell which is prohibited to be programmed. CONSTITUTION: A first bit line(BL1) is connected to a cell which is prohibited to be programmed. A second bit line is connected to a cell to be programmed. A power supply control circuit(180) supplies a first voltage to the first bit line in response with first control signal. The power supply control circuit is supplies a ground voltage to the second bit line. The power supply control circuit supplies a second voltage to the second bit line in response with second control signal.
Abstract translation: 目的：提供减少存储单元与包括其的半导体系统之间的耦合现象的存储器件，以恒定地维持禁止编程的单元的沟道电压。 构成：第一位线（BL1）连接到禁止编程的单元。 第二位线连接到要编程的单元。 电源控制电路（180）响应于第一控制信号向第一位线提供第一电压。 电源控制电路向第二位线提供接地电压。 电源控制电路响应于第二控制信号向第二位线提供第二电压。
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公开(公告)号：KR100835282B1
公开(公告)日：2008-06-05
申请号：KR1020070006945
申请日：2007-01-23
Applicant: 삼성전자주식회사
IPC: H01L27/04
CPC classification number: H01L27/0262 , H01L29/7436
Abstract: An electrostatic discharge protection device is provided to reducing a trigger voltage by increasing a current gain of a junction transistor and increasing resistance between the junction transistor and a first power supply and increasing a holding voltage through a diode. An electrostatic discharge protection apparatus includes a first n well(21), a first n+ region(31), a first p+ region(32), a second n+ region(33), a third n+ region(34), and a gate electrode(40). The first n well is formed in a p-type substrate(20). The first n+ region and the first p+ region are formed in the first n well. The second n+ region is spaced apart from the p+ region. Insulation layers(30) are inserted between the first n+ region and the p+ region, and between the p+ region and the second n+ region, respectively. The third n+ region is spaced apart from the second n+ region. The gate electrode is formed on the p-type substrate between the second n+ region and the third n+ region. A second n well is formed under the third n+ region. A third n well is spaced apart from a second p+ region. An input/output terminal is connected to the first n+ region and the first p+ region.
Abstract translation: 提供一种静电放电保护装置，通过增加结晶体管的电流增益并增加结晶体管与第一电源之间的电阻并增加通过二极管的保持电压来降低触发电压。 一种静电放电保护装置包括：第一n阱（21），第一n +区（31），第一p +区（32），第二n +区（33），第三n +区（34） （40）。 第一n阱形成在p型衬底（20）中。 第一n +区和第一p +区形成在第一n阱中。 第二n +区域与p +区域间隔开。 绝缘层（30）分别插入在第一n +区和p +区之间以及p +区和第二n +区之间。 第三n +区域与第二n +区域间隔开。 栅电极形成在p型衬底之间的第二n +区和第三n +区之间。 在第三n +区域下形成第二个n阱。 第三个n阱与第二个p +区域间隔开。 输入/输出端连接到第一n +区和第一p +区。
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公开(公告)号：KR101586047B1
公开(公告)日：2016-01-18
申请号：KR1020090025330
申请日：2009-03-25
Applicant: 삼성전자주식회사
CPC classification number: G11C16/349 , G11C16/10 , G11C16/3495
Abstract: 본발명의불휘발성메모리장치는, 복수의메모리블록들을포함하되상기메모리블록들각각은복수개의영역들로분할되는메모리셀 어레이, 그리고상기메모리블록들의소거내지프로그램주기를근거로하여프로그램될메모리블록을선택하고상기선택된메모리블록에대응되는상기복수의영역들에대한소거내지프로그램주기를근거로하여상기선택된메모리블록에적용되는프로그램방식을가변시키는제어로직을포함한다.
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公开(公告)号：KR101571763B1
公开(公告)日：2015-12-07
申请号：KR1020080065678
申请日：2008-07-07
Applicant: 삼성전자주식회사
CPC classification number: G11C16/20
Abstract: 적응적제어스킴을가지는메모리장치및 그동작방법이개시된다. 본발명의메모리장치는, 다수의그룹으로구분될수 있는메모리셀어레이, 상기다수의그룹각각에대한그룹별특성데이터셋을저장하며, 수신된어드레스신호에상응하는그룹의특성데이터셋을출력하는룩업부, 및수신된명령에따라, 상기출력된그룹특성데이터셋을이용하여상기메모리셀어레이에대한동작을제어하는스테이트머신을구비하여, 메모리셀어레이를구성하는메모리블록별또는그룹별로별도로구비된특성데이터셋을이용하여메모리블록별또는그룹별로적응적으로프로그램, 소거, 독출동작등을제어함으로써, 메모리블록별또는그룹별로동작조건을최적화시킬수 있다.
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