公开(公告)号：KR1020020094471A

公开(公告)日：2002-12-18

申请号：KR1020010032700

申请日：2001-06-12

Applicant: 삼성전자주식회사

Inventor： 정우찬

IPC: H01L21/68

Abstract: PURPOSE: A wafer alignment device for oxide layer deposition equipment is provided to align correctly a wafer on a cooling plate by forming centering pins on a concentric circle of the wafer according to a predetermined interval. CONSTITUTION: A plurality of centering pins(20) are formed along an outer circumference of a flat cooling plate(10). The centering pins(20) are formed on the outside of the flat cooling plate(10) according to a predetermined interval. A wafer(30) is loaded on the flat cooling plate(10). The number of the centering pins(20) is seven. The six centering pins(20) are used for supporting end portions of a circular arc of the wafer(30). The remaining centering pin(20) is located to a center portion of a flat zone(31) of the wafer(30). The wafer(30) is aligned by the six centering pins(20).

Abstract translation: 目的：提供一种用于氧化物层沉积设备的晶片对准装置，用于根据预定间隔在晶片的同心圆上形成定心销，使晶片正确地对准冷却板。 构成：沿扁平冷却板（10）的外圆周形成多个定心销（20）。 定心销（20）按照预定间隔形成在平板冷却板（10）的外侧上。 将晶片（30）装载在平坦冷却板（10）上。 定心销（20）的数量为7。 六个定心销（20）用于支撑晶片（30）的圆弧的端部。 剩余的定心销（20）位于晶片（30）的平坦区域（31）的中心部分。 晶片（30）通过六个定心销（20）对准。

公开(公告)号：KR1020020044210A

公开(公告)日：2002-06-15

申请号：KR1020000073192

申请日：2000-12-05

Applicant: 삼성전자주식회사

Inventor： 정우찬 ,  이승무 ,  전진호 ,  최병덕 ,  임전식 ,  이종승

IPC: H01L21/31

Abstract: PURPOSE: A method for fabricating an insulation layer of a semiconductor device is provided to reduce sheet resistance of a plate electrode, by sufficiently increasing an interval of divert time of B-source gas and P-source gas until a mass flow controller(MFC) is stabilized. CONSTITUTION: An insulation substrate(10) having a capacitor composed of a storage electrode(20), a dielectric layer(30) and a plate electrode(40) is prepared. A barrier layer(45) of an insulation material having no fluidity is formed on the resultant structure. The B-source gas and the P-source gas are diverted for 10-15 seconds to stabilize gas flow. An insulation layer(50) of a boron phosphorous silicate glass(BPSG) material is formed on the barrier layer by using a semi-atmospheric chemical vapor deposition(SACVD) process.

Abstract translation: 目的：提供一种用于制造半导体器件的绝缘层的方法，通过充分增加B源气体和P源气体的转移时间的间隔直到质量流量控制器（MFC）为止，以降低平板电极的薄层电阻， 稳定了 制备具有由存储电极（20），电介质层（30）和平板电极（40）构成的电容器的绝缘基板（10）。 在所得结构上形成没有流动性的绝缘材料的阻挡层（45）。 B源气体和P源气体转向10-15秒以稳定气体流动。 通过使用半大气化学气相沉积（SACVD）工艺在阻挡层上形成磷硅酸玻璃（BPSG）材料的绝缘层（50）。

公开(公告)号：KR1020010068598A

公开(公告)日：2001-07-23

申请号：KR1020000000596

申请日：2000-01-07

Applicant: 삼성전자주식회사

Inventor： 정우찬 ,  최병덕 ,  최철환

IPC: H01L21/205

Abstract: PURPOSE: A CVD(Chemical Vapor Deposition) apparatus for manufacturing a semiconductor is provided to be capable of shortening work period and enhancing remarkably productivity by mounting a plurality of process chambers on both sides of a transfer chamber and stacking three load racks within a load rack chamber. CONSTITUTION: A moving unit(21) for loading/unloading a wafer is equipped in a transfer chamber(20). At least three process chambers(31,32,33) are respectively mounted on both sides and a rear side of the transfer chamber(20). The wafer loaded/unloaded in the process chambers(31,32,33) is stored in at least three load racks(41), which are stacked in a load rack chamber(40). In this structure, the wafers(W) within the process chambers(31,32,33) are unloaded toward the load racks(41) within the chamber(40) or loaded inversely.

Abstract translation: 目的：提供一种用于制造半导体的CVD（化学气相沉积）装置，其能够缩短工作周期并且通过在传送室的两侧安装多个处理室并且将三个负载架堆叠在负载架内来提高显着的生产率 室。 构成：用于装载/卸载晶片的移动单元（21）装备在传送室（20）中。 至少三个处理室（31,32,33）分别安装在传送室（20）的两侧和后侧。 装载/卸载在处理室（31,32,33）中的晶片被存储在至少三个负载架（41）中，堆叠在负载架室（40）中。 在这种结构中，处理室（31,32,33）内的晶片（W）朝向室（40）内的负载架（41）卸载或反向加载。