반도체 유동성 산화막 증착 공정의 수율 향상 방법
    1.
    发明公开
    반도체 유동성 산화막 증착 공정의 수율 향상 방법 无效
    改善半导体中氧化物存在沉积过程的方法

    公开(公告)号:KR1020020092683A

    公开(公告)日:2002-12-12

    申请号:KR1020010031458

    申请日:2001-06-05

    Abstract: PURPOSE: A method for improving a yield of a deposition process of a flowing oxide in a semiconductor is provided to improve productivity, prevent a loss of etching solution, and lengthen a lifetime of a motor by optimizing a back side cleaning time and a drying time of a wafer. CONSTITUTION: The seventh process(18) is a process for rising a back side of a wafer. A flowing oxide layer is deposited on a wafer by using a spin method. The eleventh process(22) is a process for drying the back side of the wafer. Each predetermined processing time is determined in the seventh process(18) and the eleventh process(22). In the seventh process(18), an injecting time of the etching solution is determined within 10 to 19 seconds and only a BR valve is in the opening state. In the eleventh process(22), the dry time is determined within 10 to 19 seconds and only a CR valve is in the opening state.

    Abstract translation: 目的:提供一种用于提高半导体中流动的氧化物的沉积过程的产率的方法,以通过优化背面清洁时间和干燥时间来提高生产率,防止蚀刻溶液的损失和延长电机的寿命 的晶片。 构成:第七工序(18)是使晶片背面上升的工序。 通过使用旋转方法将流动的氧化物层沉积在晶片上。 第十二工序(22)是干燥晶片的背面的工序。 在第七过程(18)和第十一处理(22)中确定每个预定的处理时间。 在第七工序(18)中,在10〜19秒内确定蚀刻溶液的注入时间,只有BR阀处于打开状态。 在第十一工序(22)中,干燥时间在10〜19秒内确定,只有CR阀处于打开状态。

    반도체 제조 설비
    2.
    发明公开
    반도체 제조 설비 无效
    制造半导体设备

    公开(公告)号:KR1020020010303A

    公开(公告)日:2002-02-04

    申请号:KR1020000043952

    申请日:2000-07-29

    Inventor: 정우찬 임전식

    Abstract: PURPOSE: Equipment for manufacturing a semiconductor is provided to increase productivity by remarkably decreasing the number of processes performed in atmospheric pressure chemical vapor deposition(APCVD) equipment, and to greatly shorten the cleaning period and time of a process belt by minimizing contamination of the process belt. CONSTITUTION: A wafer is loaded to a loader(100). The wafer is supplied to the loader which transfers the wafer. The second conveyer is supplied with the wafer from the first conveyer while closed, and forms a predetermined thin film on the wafer by reaction gas. The wafer is loaded from the second conveyer to the third conveyer. A process unit(200) includes the first, second and third conveyers. The wafer is loaded from the third conveyer to an unloader(300). The number of the wafers simultaneously loaded to the first, second and third conveyers has a multiple relation with the number of whole wafers received in the loader.

    Abstract translation: 目的:提供用于制造半导体的设备,通过显着降低在大气压化学气相沉积(APCVD)设备中进行的工艺数量来提高生产率,并通过最小程度地减少工艺带的污染来大大缩短工艺带的清洁周期和时间 带。 构成:将晶片装载到装载机(100)中。 晶片被提供给传送晶片的装载器。 第二输送机在封闭时从第一输送机供给晶片,并通过反应气体在晶片上形成预定的薄膜。 晶片从第二输送机装载到第三输送机。 处理单元(200)包括第一,第二和第三输送机。 晶片从第三输送机装载到卸载机(300)。 同时装载到第一,第二和第三输送机的晶片的数量与在装载机中接收的整个晶片的数量具有多重关系。

    절연막 제조 방법 및 반도체 장치의 제조 방법
    3.
    发明公开
    절연막 제조 방법 및 반도체 장치의 제조 방법 失效
    制造绝缘层的方法和制造半导体器件的方法

    公开(公告)号:KR1020020081735A

    公开(公告)日:2002-10-30

    申请号:KR1020010021067

    申请日:2001-04-19

    CPC classification number: C23C16/401 C23C16/56

    Abstract: PURPOSE: A method for fabricating an insulating layer and a method for fabricating a semiconductor device are provided to fabricate a BPSG(Boron Phosphorus Silicate Glass) layer as the insulating layer by using an oxygen gas, a nitrogen gas, a helium gas, TEOD(Tetra-Ethyl-Ortho-Silicate), TEB(Tri-Ethyl-Borate), and TEPO(Tri-Ethyl-Phosphaste). CONSTITUTION: A substrate(20) is located in the inside of a chamber. An oxygen gas of 4,500sccm, a nitrogen gas of 3,000sccm, and a helium gas of 4,000sccm are provided to the inside of the chamber. A pressure atmosphere is formed in the inside of the chamber by using a pumping member connected with the chamber. The oxygen gas of 9,500sccm, the nitrogen gas of 3,000sccm, and the helium gas of 4,000sccm are provided to the inside of the chamber under the pressure atmosphere. The pressure atmosphere is stabilized after an operation of the pumping member is stopped. A BPSG layer(22) as an insulating layer is formed by providing TEOD of 800sccm, TEB of 170sccm, and TEPO of 55sccm to the inside of the chamber under a process atmosphere including the gas atmosphere, the pressure atmosphere, and a stabilization atmosphere.

    Abstract translation: 目的:制造绝缘层的方法和制造半导体器件的方法被提供以通过使用氧气,氮气,氦气,TEOD(制造绝缘层)制造BPSG(硼硅磷酸盐玻璃)层作为绝缘层 四乙基 - 正硅酸盐),TEB(三乙基硼酸盐)和TEPO(三乙基 - 磷酸盐)。 构成:衬底(20)位于腔室的内部。 将4,500sccm的氧气,3,000sccm的氮气和4000sccm的氦气提供到室的内部。 通过使用与室连接的泵送构件,在室的内部形成压力气氛。 将950sccm的氧气,3,000sccm的氮气和4000sccm的氦气在压力气氛下向室内提供。 在泵送构件的操作停止之后,压力气氛稳定。 通过在包括气体气氛,压力气氛和稳定气氛的处理气氛下,向室内提供800sccm的TEOD,170sccm的TEB和55sccm的TEPO,形成作为绝缘层的BPSG层(22)。

    화학 기상 증착 장비
    4.
    发明公开
    화학 기상 증착 장비 无效
    化学蒸气沉积设备

    公开(公告)号:KR1020010091554A

    公开(公告)日:2001-10-23

    申请号:KR1020000013384

    申请日:2000-03-16

    Abstract: PURPOSE: CVD(chemical vapor deposition) equipment is provided to exactly control supply quantities of TEPO(triethylphosphate) by independent controlling carrier gases using a carrier gas flow controller. CONSTITUTION: The CVD equipment comprises a plurality of containers(206,208,210) for containing liquid sources, a plurality of evaporation units(230,232,234) corresponding to the containers, a mixing part(260), and a processing chamber(270). The CVD equipment further includes a plurality of carrier gas flow controllers(240,242,244) independently connected to an exhaust outlet of the containers(206,208,210), thereby independently controlling quantities of the exhausted source materials. The processing chamber(270) is formed to a BPSG(boro phosphor silicate glass) film and the containers(206,208,210) is contained to a TEPO.

    Abstract translation: 目的:提供CVD(化学气相沉积)设备,通过使用载气流量控制器独立控制载气精确控制TEPO(磷酸三乙酯)的供应量。 构成:CVD设备包括用于容纳液体源的多个容器(206,208,210),对应于容器的多个蒸发单元(230,232,234),混合部分(260)和处理室(270)。 CVD设备还包括独立地连接到容器(206,208,210)的排气出口的多个载气流量控制器(240,242,244),从而独立地控制排出的源材料的量。 处理室(270)形成为BPSG(硼硅磷酸盐玻璃)膜,容器(206,208,210)被包含在TEPO中。

    반도체 제조설비의 인젝터 노즐
    5.
    发明公开
    반도체 제조설비의 인젝터 노즐 无效
    喷射器半导体制造系统喷嘴

    公开(公告)号:KR1020000008540A

    公开(公告)日:2000-02-07

    申请号:KR1019980028411

    申请日:1998-07-14

    Inventor: 임전식 조영수

    Abstract: PURPOSE: An injector nozzle for fabricating semiconductor devices is provided to improve a uniformity of coated film thickness by differentiating the spaced distance between a nozzle and a wafer according to temperature gradient. CONSTITUTION: The injector nozzle(200) of pipe structure includes a source gas supplying opening(201) and a plurality of injection openings(202) spaced apart from each other. The spaced distance between the injection openings(202) and a wafer(230) is different each other according to the temperature gradients. That is, the spaced distance(a) at the center portion of the wafer(230) having relatively high temperature is longer than that(b) of the edge portions of the wafer(230) having relatively low temperature. Thereby, it is possible to improve the uniformity of coated film formed on the wafer(230).

    Abstract translation: 目的:提供用于制造半导体器件的注射器喷嘴,以通过根据温度梯度区分喷嘴和晶片之间的间隔距离来改善涂膜厚度的均匀性。 构成:管结构的喷射器喷嘴(200)包括源气体供给口(201)和彼此间隔开的多个喷射口(202)。 注射开口(202)和晶片(230)之间的间隔距离根据温度梯度彼此不同。 也就是说,具有相对较高温度的晶片(230)的中心部分处的间隔距离(a)比具有较低温度的晶片(230)的边缘部分的距离(a)长。 由此,可以提高在晶片(230)上形成的涂膜的均匀性。

    비정질 탄소막 형성 방법 및 이를 이용한 패턴 형성 방법
    7.
    发明公开
    비정질 탄소막 형성 방법 및 이를 이용한 패턴 형성 방법 无效
    形成非晶碳层的方法和使用其形成图案的方法

    公开(公告)号:KR1020100112070A

    公开(公告)日:2010-10-18

    申请号:KR1020100010272

    申请日:2010-02-04

    Abstract: PURPOSE: A method for forming an amorphous carbon film and a method for forming patterns using the same are provided to manufacture a semiconductor device including fine patterns using an amorphous carbon film with the superior planarity as a hard mask film. CONSTITUTION: A susceptor(12) is located in a depositing chamber(10) in order to support a substrate. A guide ring(14) is located on the edge side of the susceptor in order to guide the substrate. A heater(16) is located in the susceptor. A shower head(18) is located to be opposite with the susceptor and is connected with a depositing gas supplying unit(22) which is located on the outside of the depositing chamber. High frequency power(20) is connected with the shower head.

    Abstract translation: 目的:提供一种形成非晶碳膜的方法和使用其形成图案的方法,以制造具有使用具有优异平面度的非晶碳膜作为硬掩模膜的精细图案的半导体器件。 构成:为了支撑衬底,感受体(12)位于沉积室(10)中。 引导环(14)位于基座的边缘侧,以引导基板。 加热器(16)位于基座中。 淋浴头(18)位于与基座相对的位置,并与位于沉积室外侧的沉积气体供应单元(22)连接。 高频电源(20)与喷头连接。

    디클로로 실란의 이상성장 제어가 가능한 두개의 층을갖는 반도체 박막형성방법
    8.
    发明授权
    디클로로 실란의 이상성장 제어가 가능한 두개의 층을갖는 반도체 박막형성방법 有权
    디클로로실란의이상성장제어가가능한두개의층을갖는반도체박막형성방

    公开(公告)号:KR100379108B1

    公开(公告)日:2003-04-07

    申请号:KR1020010016959

    申请日:2001-03-30

    Abstract: PURPOSE: A method for fabricating a semiconductor thin film having two layers capable of controlling an abnormal growth of dichloro-silane is provided to eliminate or decrease an abnormal growth of a lower polysilicon layer, by stacking the lower polysilicon layer at a temperature in which the lower polysilicon is not crystallized and by preventing silicon from being injected to the lower polysilicon layer. CONSTITUTION: A diffusion process is performed at the first temperature in which polysilicon is not crystallized so that a polysilicon layer is formed on a substrate. The first temperature for forming the polysilicon layer is increased to the second temperature. The polysilicon layer is flushed to form a transition layer by using the first flush material(S106). The polysilicon layer is flushed to form the second material layer on the polysilicon layer by using the second flush material(S108). The transition layer provides an adhesion characteristic between the second material layer and the polysilicon. The bulk of the second material layer is formed on the transition layer by using a composition of the first and second flush materials. The bulk of the second material layer is flushed to remove impurities by using the second flush material. The bulk of the second material layer is flushed to decrease stress between the polysilicon layer and the second material layer by using the first flush material(S116).

    Abstract translation: 目的:提供一种制造具有能够控制二氯硅烷的异常生长的两层的半导体薄膜的方法,以消除或减少下多晶硅层的异常生长,通过在下述温度下堆叠下多晶硅层: 下多晶硅不结晶,并且通过防止硅被注入下多晶硅层。 构成:扩散工艺是在多晶硅不结晶的第一温度下进行的,以便在衬底上形成多晶硅层。 用于形成多晶硅层的第一温度增加到第二温度。 通过使用第一冲洗材料冲洗多晶硅层以形成过渡层(S106)。 通过使用第二冲洗材料冲洗多晶硅层以在多晶硅层上形成第二材料层(S108)。 过渡层提供第二材料层和多晶硅之间的粘附特性。 通过使用第一冲洗材料和第二冲洗材料的组合物在过渡层上形成大部分第二材料层。 通过使用第二冲洗材料冲洗大部分第二材料层以去除杂质。 通过使用第一冲洗材料冲洗第二材料层的主体以减小多晶硅层和第二材料层之间的应力(S116)。

    챔버 플라즈마 클리닝 방법
    9.
    发明公开
    챔버 플라즈마 클리닝 방법 无效
    清洁室的等离子体的方法

    公开(公告)号:KR1020030002465A

    公开(公告)日:2003-01-09

    申请号:KR1020010038082

    申请日:2001-06-29

    Abstract: PURPOSE: A method for cleaning plasma of a chamber is provided to reduce a processing time by setting up a ratio of WF6/DCS gas as 7/180, a time for forming processing atmosphere of a chamber as 240 seconds, and a time for cleaning the chamber as 900 seconds. CONSTITUTION: A cleaning recipe includes 20 steps(P/D, NF3, RF1, RF2, P/D, AR, P/D, AR, P/D, AR, P/D, AR, P/D, COAT1, COAT2, P/D, AR, P/D, AR, and P/D) performed between the first pump-down operation and the next pump-down operation. Each step has 15 operating conditions(Hivac Seq, Time, Pressure, MFC1 AR, MFC2 SiH4, MFC3 DCS, MFC4 AR, MFC5 AR, MFC6 WF6, MFC7 SP, ACE, MFC8 NF3, LF RF Power, HF RF Power, Vent Bits, and Ramp Bits) between Hivac Seq for forming a high vacuum state of the inside of a chamber and Ramp Bits for heating the inside of the chamber. The RF1 and the RF2 perform a chamber cleaning process. The P/D removes the remaining gas from the inside of the chamber. The AR is an Ar purge process. The COAT1 and COAT2 perform processing atmosphere after the chamber cleaning process is performed.

    Abstract translation: 目的:提供一种清洗室的等离子体的方法,通过将WF6 / DCS气体的比例设置为7/180,将室的处理气氛形成时间为240秒,清洗时间缩短处理时间 房间900秒。 规定:清洁配方包括20个步骤(P / D,NF3,RF1,RF2,P / D,AR,P / D,AR,P / D,AR,P / D,AR,P / D,COAT1,COAT2 ,P / D,AR,P / D,AR和P / D)。 每个步骤有15个操作条件(Hivac Seq,Time,Pressure,MFC1 AR,MFC2 SiH4,MFC3 DCS,MFC4 AR,MFC5 AR,MFC6 WF6,MFC7 SP,ACE,MFC8 NF3,LF RF功率,HF RF功率, 和斜坡位),用于形成室内的高真空状态和用于加热室内的斜坡位。 RF1和RF2执行腔室清洁过程。 P / D从室内除去剩余的气体。 AR是Ar清除过程。 COAT1和COAT2在进行室清洁处理后进行处理气氛。

    고용량을 갖는 캐패시터의 제조방법 및 이를 이용한 반도체 소자의 제조방법
    10.
    发明公开
    고용량을 갖는 캐패시터의 제조방법 및 이를 이용한 반도체 소자의 제조방법 失效
    制造具有高容量的电容器的方法和使用其制造半导体器件的方法

    公开(公告)号:KR1020010019207A

    公开(公告)日:2001-03-15

    申请号:KR1019990035499

    申请日:1999-08-25

    Inventor: 임전식 서태욱

    CPC classification number: H01L28/87 H01L28/84

    Abstract: PURPOSE: A method for manufacturing a capacitor having high capacitance is provided to increase capacitance of the capacitor used in a memory device by increasing an area of a storage electrode, and to further increase capacitance by forming hemispherical grain(HSG) silicon layer in or on the storage electrode. CONSTITUTION: A sacrificial layer includes a plurality of oxide layers in which adjacent oxide layers have different etch rates according to kinds of impurities contained on a substrate or difference of impurity density. At least one hole is formed in the sacrificial layer. A roughness part is formed on a sidewall of the sacrificial layer exposed by the hole. The first conductive layer is formed on the sidewall of the sacrificial layer. A dielectric layer(135) and the second conductive layer are sequentially formed on the first conductive layer.

    Abstract translation: 目的:提供一种用于制造具有高电容的电容器的方法,以通过增加存储电极的面积来增加存储器件中使用的电容器的电容,并且通过在其中或之上形成半球形晶粒(HSG)硅层来进一步增加电容 存储电极。 构成:牺牲层包括多个氧化物层,其中相邻的氧化物层根据衬底上杂质的种类或杂质浓度的不同而具有不同的蚀刻速率。 在牺牲层中形成至少一个孔。 粗糙部分形成在由孔暴露的牺牲层的侧壁上。 第一导电层形成在牺牲层的侧壁上。 介电层(135)和第二导电层依次形成在第一导电层上。

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