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公开(公告)号：KR1020140013401A
公开(公告)日：2014-02-05
申请号：KR1020120080246
申请日：2012-07-23
Applicant: 삼성전자주식회사
CPC classification number: G11C16/24 , G11C11/5642 , G11C16/0483 , G11C16/26
Abstract: A memory device according to the technical object of the present invention includes a memory cell array which includes a plurality of memory cells and a page buffer unit which performs the logic operation of read data based on reading directions in the different voltage levels and data which is successively read in different voltage levels with regard to the memory cells. [Reference numerals] (10A) Memory controller; (11) ECC processor; (12) Read voltage control unit; (20A) Memory device; (21) Memory cell array; (22) Page buffer unit
Abstract translation: 根据本发明的技术目的的存储装置包括：存储单元阵列，其包括多个存储单元;以及页缓冲器单元，其基于不同电压电平的读取方向进行读取数据的逻辑运算， 相对于存储单元依次读取不同的电压电平。 （附图标记）（10A）存储器控制器; （11）ECC处理器; （12）读电压控制单元; （20A）存储器件; （21）存储单元阵列; （22）页面缓冲单元
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公开(公告)号：KR1020130125426A
公开(公告)日：2013-11-19
申请号：KR1020120048910
申请日：2012-05-09
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418
Abstract: A program method of a non-volatile memory device including multi-level cells which store multi-bit data performs a free program which programs the multi-level cells in mediate states. The method performs a main program which programs the multi-level cells in program states corresponding to the multi-bit data.
Abstract translation: 包括存储多位数据的多级单元的非易失性存储器件的程序方法执行一个在中间状态下编程多级单元的空闲程序。 该方法执行主程序，该程序对应于多位数据的程序状态编程多级单元。
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公开(公告)号：KR1020130096489A
公开(公告)日：2013-08-30
申请号：KR1020120017986
申请日：2012-02-22
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0246 , G06F11/1068 , G11C7/1006 , G11C11/5628 , G11C16/10 , G11C2211/5641
Abstract: PURPOSE: Memory system and programming method thereof are provided to improve the performance by setting up data for main program operation in an optimal main program method. CONSTITUTION: Whether a required main program operation is normal main program operation or not is judged (S400). When the required main program operation is judged as normal main program operation, a normal main program method is selected (S410). When the required main program operation is not judged as normal main program operation, the time for executing the required main program operation is calculated (S420). According to the calculated time, one of the plurality of main program schemes is selected (S430).
Abstract translation: 目的：提供存储器系统及其编程方法，通过在最佳主程序方法中设置主程序运行的数据来提高性能。 判定：是否要求主程序运行是否正常主程序运行（S400）。 当所需的主程序操作被判断为正常的主程序操作时，选择正常的主程序方法（S410）。 当所需的主程序操作不被判断为正常的主程序操作时，计算执行所需的主程序操作的时间（S420）。 根据计算出的时间，选择多个主程序方案之一（S430）。
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公开(公告)号：KR1020130079853A
公开(公告)日：2013-07-11
申请号：KR1020120000592
申请日：2012-01-03
Applicant: 삼성전자주식회사
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/30
Abstract: PURPOSE: A non-volatile memory device and a memory system including the same are provided to improve the read operation speed of a partial page by implementing as an all bit line. CONSTITUTION: A memory cell array (110) is connected to multiple bit lines and multiple word lines. A page buffer circuit (130) senses memory cells connected to the selected word line through the multiple bit lines. A voltage generator (160) provides a read voltage to the selected word line. A control logic (150) controls the page buffer circuit and the voltage generator to sense the memory cells connected to the selected word line. The number of memory cells which are simultaneously sensed in a first read mode and a second read mode are different.
Abstract translation: 目的：提供一种非易失性存储器件和包括该非易失性存储器件的存储器系统，以通过实现全部位线来提高部分页面的读取操作速度。 构成：存储单元阵列（110）连接到多个位线和多个字线。 页面缓冲电路（130）通过多个位线来感测连接到所选字线的存储单元。 电压发生器（160）向所选择的字线提供读取电压。 控制逻辑（150）控制页面缓冲电路和电压发生器来感测连接到所选字线的存储单元。 在第一读取模式和第二读取模式下同时感测的存储器单元的数量是不同的。
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45.发明公开
公开(公告)号：KR1020130060791A
公开(公告)日：2013-06-10
申请号：KR1020110127043
申请日：2011-11-30
Applicant: 삼성전자주식회사
CPC classification number: G11C16/06 , G06F11/1072 , G06F12/0246 , G06F2212/7211 , G11C11/5621 , G11C16/349 , G11C16/3495 , G11C2029/0411
Abstract: PURPOSE: A memory system including abrasion control logic, a data storage device, a memory card, and a solid state drive are provided to improve the performance of the memory system by reducing an ECC error rate and an increase rate of an erasing loop number. CONSTITUTION: A memory system(100) includes a non-volatile memory(110) and an abrasion control logic(126). The non-volatile memory has a user area and a buffer area. The abrasion control logic controls an operation for converting a part of a memory block in the user area into the buffer area based on abrasion information of the non-volatile memory.
Abstract translation: 目的：提供包括磨损控制逻辑，数据存储装置，存储卡和固态驱动器的存储器系统，以通过减少ECC错误率和擦除循环数的增加速率来提高存储器系统的性能。 构成：存储系统（100）包括非易失性存储器（110）和磨损控制逻辑（126）。 非易失性存储器具有用户区和缓冲区。 磨损控制逻辑基于非易失性存储器的磨损信息来控制用于将用户区域中的一部分存储块转换为缓冲区域的操作。
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Patent Agency Ranking46.发明公开
公开(公告)号：KR1020130057877A
公开(公告)日：2013-06-03
申请号：KR1020110123847
申请日：2011-11-24
Applicant: 삼성전자주식회사
CPC classification number: G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C29/00
Abstract: PURPOSE: A method of operating a non-volatile memory device and a memory system including the same are provided to rapidly recover read errors regarding a reading operation by rapidly calculating the variation of data. CONSTITUTION: First data read from a target page is stored in a first page buffer(41) using a first read voltage level. Second data read from the target page is stored in a second page buffer(43) using a second read voltage level. Third data stored in a third page buffer(45) is changed through the first data transmitted from the first page buffer and the second data transmitted from the second page buffer in order to generate the same data as bit-wise XOR data.
Abstract translation: 目的：提供一种操作非易失性存储器件和包括其的存储器系统的方法，通过快速计算数据的变化来快速恢复关于读取操作的读取错误。 构成：使用第一读取电压电平将从目标页面读取的第一数据存储在第一页缓冲器（41）中。 从目标页面读取的第二数据使用第二读取电压电平存储在第二页缓冲器（43）中。 通过从第一页缓冲器发送的第一数据和从第二页缓冲器发送的第二数据来改变存储在第三页缓冲器（45）中的第三数据，以便生成与逐位异或数据相同的数据。
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公开(公告)号：KR1020120097829A
公开(公告)日：2012-09-05
申请号：KR1020110017293
申请日：2011-02-25
Applicant: 삼성전자주식회사
CPC classification number: G11C7/22 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C8/18
Abstract: PURPOSE: A memory system and a controlling method thereof are provided to efficiently prevent the overlap of a peak current from a plurality of semiconductor memory devices and minimize the operation delay of each semiconductor memory device. CONSTITUTION: Memory devices(MDEV1-MDEVn) include an internal clock generator and a memory. The internal clock generator(IGEN) generates an internal clock by synchronizing with a processor clock in response to the processor clock received from a controller(CNT). A memory is synchronized with the internal clock to generate a peak current. Two or more memory devices generate the internal clock which is activated in a different edge of the processor clock.
Abstract translation: 目的：提供一种存储器系统及其控制方法，以有效地防止来自多个半导体存储器件的峰值电流的重叠，并使每个半导体存储器件的操作延迟最小化。 规定：存储器件（MDEV1-MDEVn）包括内部时钟发生器和存储器。 内部时钟发生器（IGEN）响应于从控制器（CNT）接收的处理器时钟，与处理器时钟同步来产生内部时钟。 存储器与内部时钟同步以产生峰值电流。 两个或多个存储器件产生在处理器时钟的不同边缘被激活的内部时钟。
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公开(公告)号：KR1020110066697A
公开(公告)日：2011-06-17
申请号：KR1020090123446
申请日：2009-12-11
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0246 , G06F2212/7201
Abstract: PURPOSE: An address mapping table management method and a memory device thereof are provided to extend the lifetime of the memory device and improve the performance by managing an address mapping table to reduce the elimination frequency of the memory device. CONSTITUTION: The first memory cell array(10) stores data. A wear-leveling controller(40) manages a ware-level. The second memory cell array(60) stores an address mapping table. If a conversion physical address mapped in a physical address of the first memory cell array is changed, a memory control unit(30) stores the movement quantity of an address which has to be moved based on the conversion physical address prior to the change in the address mapping table. The memory control unit maps the physical address to the changed conversion physical address with reference to the address mapping table.
Abstract translation: 目的：提供地址映射表管理方法及其存储器件，以延长存储器件的寿命并通过管理地址映射表来提高性能，以减少存储器件的消除频率。 构成：第一个存储单元阵列（10）存储数据。 磨损均衡控制器（40）管理物品级。 第二存储单元阵列（60）存储地址映射表。 如果映射到第一存储单元阵列的物理地址中的转换物理地址改变，则存储器控制单元（30）根据转换物理地址在存储器单元阵列的改变之前存储必须移动的地址的移动量 地址映射表。 存储器控制单元参考地址映射表将物理地址映射到改变的转换物理地址。
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公开(公告)号：KR1020080065116A
公开(公告)日：2008-07-11
申请号：KR1020070002103
申请日：2007-01-08
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628
Abstract: A multi level cell flash memory device and a program method thereof are provided to perform flexible program for various requirements of a system, by performing the program regardless of the sequence of bits of multi bit data. According to a program method of a multi level cell flash memory device, a memory cell selected through plural program procedures is programmed with multi bit data(11,10,01,00). Data to be stored in the selected memory cell in the present program procedure is determined by the data of the selected memory cell and the present program procedure. According to the present program procedure, an address of bits programmed in the present program procedure is detected. The data of the selected memory cell is read. Target data is determined by referring to the detected address and the data of the selected memory cell.
Abstract translation: 提供多级单元闪存器件及其程序方法，通过执行程序来执行用于系统的各种要求的灵活程序，而不管多位数据的位序列如何。 根据多电平单元闪存器件的编程方法，通过多个程序程序选择的存储器单元用多位数据（11,10,01,00）进行编程。 要存储在当前程序过程中的所选存储单元中的数据由所选存储单元的数据和当前的程序程序确定。 根据本程序程序，检测在本程序程序中编程的位地址。 读取所选存储单元的数据。 通过参考检测到的地址和所选存储单元的数据来确定目标数据。
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公开(公告)号：KR100813629B1
公开(公告)日：2008-03-14
申请号：KR1020070005259
申请日：2007-01-17
Applicant: 삼성전자주식회사
Abstract: An advanced sector protection scheme is provided to improve convenience and stability by restricting write operation for write protection state of sectors through a master cell. A memory cell array is constituted with sectors. A read/write circuit performs read and write operations of the memory cell array. A write protection control block(700) generates a write protection flag signal for a sector to be written. A control logic operates in response to the write protection flag signal, and controls the read/write circuit to perform write operation for the sector to be written selectively. The write protection control block includes a latch circuit(710), a cell array(720) and a check circuit(790). The latch circuit stores write state or write protection state of each sector temporarily. The cell array stores write state or write protection state of each sector permanently. The check circuit outputs the write protection flag signal.
Abstract translation: 提供先进的扇区保护方案，通过限制通过主单元的扇区写保护状态的写操作来提高便利性和稳定性。 存储单元阵列由扇区构成。 读/写电路执行存储单元阵列的读和写操作。 写保护控制块（700）为要写入的扇区产生写保护标志信号。 控制逻辑响应于写保护标志信号进行操作，并且控制读/写电路对要写入的扇区进行选择性的写操作。 写保护控制块包括锁存电路（710），单元阵列（720）和检查电路（790）。 锁存电路临时存储每个扇区的写状态或写保护状态。 单元阵列永久地存储每个扇区的写状态或写保护状态。 检查电路输出写保护标志信号。
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