公开(公告)号：KR1020130081950A

公开(公告)日：2013-07-18

申请号：KR1020120003079

申请日：2012-01-10

Applicant: 삼성전자주식회사

Inventor： 허진성 ,  박성준 ,  변경은 ,  서형석 ,  송현재 ,  양희준 ,  정현종

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78684 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/1606

Abstract: PURPOSE: A three dimensional switching element is provided to increase on-current by forming a semiconductor layer, a graphene layer, a gate insulating layer and a gate in a three dimensional lamination structure. CONSTITUTION: A first electrode and a second electrodue (11,12) are formed on a substrate. A semiconductor layer (13) and a graphene layer (14) are formed between the first electrode and the second electrode. The graphene layer is formed to surround an end of the semiconductor layer. A gate insulating layer (15) is formed to surround the graphene layer. A gate (16) is formed to surround the gate insulating layer.

Abstract translation: 目的：提供三维开关元件以通过在三维层压结构中形成半导体层，石墨烯层，栅极绝缘层和栅极来增加导通电流。 构成：在基板上形成第一电极和第二电极（11,12）。 在第一电极和第二电极之间形成半导体层（13）和石墨烯层（14）。 形成石墨烯层以包围半导体层的端部。 形成栅极绝缘层（15）以包围石墨烯层。 栅极（16）形成为围绕栅极绝缘层。

公开(公告)号：KR1020130022852A

公开(公告)日：2013-03-07

申请号：KR1020110085818

申请日：2011-08-26

Applicant: 삼성전자주식회사

Inventor： 허진성 ,  박성준 ,  정현종 ,  송현재 ,  양희준 ,  서형석

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/66045 ,  H01L29/78684

Abstract: PURPOSE: An inverter logic device including a graphene field effect transistor with a tunable barrier is provided to prevent a graphene defect in a graphene nanoribbon channel forming process of a graphene patterning process by forming an energy gap between an electrode and a graphene channel using a semiconductor barrier. CONSTITUTION: A gate oxide layer(320) is formed on a substrate(310). A first graphene layer(331) and a second graphene layer(332) are separately formed on the gate oxide layer. A first electrode(351) and a first semiconductor layer(341) are separately formed on the first graphene layer. A second electrode(352) and a second semiconductor layer(342) are separately formed on the second graphene layer. A first semiconductor layer and a second semiconductor layer are doped with an n-type impurity and a p-type impurity, respectively. An output electrode(370) covers the first semiconductor layer and the second semiconductor layer.

Abstract translation: 目的：提供一种包括具有可调屏障的石墨烯场效应晶体管的逆变器逻辑器件，以通过使用半导体在电极和石墨烯通道之间形成能隙来防止石墨烯纳米管通道形成石墨烯图案化过程中的石墨烯缺陷 屏障。 构成：在衬底（310）上形成栅氧化层（320）。 第一石墨烯层（331）和第二石墨烯层（332）分别形成在栅极氧化物层上。 在第一石墨烯层上分别形成第一电极（351）和第一半导体层（341）。 在第二石墨烯层上分别形成第二电极（352）和第二半导体层（342）。 第一半导体层和第二半导体层分别掺杂有n型杂质和p型杂质。 输出电极（370）覆盖第一半导体层和第二半导体层。

公开(公告)号：KR1020120137053A

公开(公告)日：2012-12-20

申请号：KR1020110056341

申请日：2011-06-10

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 송현재 ,  조병진 ,  서순애 ,  신우철

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/778 ,  H01L29/1606 ,  H01L29/513

Abstract: PURPOSE: A graphene electronic device having a multi-layered gate insulating layer is provided to improve electrical characteristics of a grapheme by forming a gate insulating layer of a double layer between a graphene channel layer and a gate electrode. CONSTITUTION: A conductive substrate serves as a gate electrode. A gate insulating layer(120) is arranged on the substrate. A graphene channel layer(130) is formed on the gate insulating layer. A source electrode(141) and a drain electrode(142) are arranged on both ends of the graphene channel layer. The gate insulating layer comprises and inorganic material insulating layer and an organic compound insulating layer on the inorganic material insulating layer.

Abstract translation: 目的：提供具有多层栅极绝缘层的石墨烯电子器件，以通过在石墨烯通道层和栅电极之间形成双层栅极绝缘层来改善图形的电特性。 构成：导电衬底用作栅电极。 栅极绝缘层（120）布置在衬底上。 在栅极绝缘层上形成石墨烯沟道层（130）。 源极电极（141）和漏电极（142）布置在石墨烯通道层的两端。 栅绝缘层包括无机材料绝缘层和无机材料绝缘层上的有机化合物绝缘层。