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公开(公告)号：KR1020130102399A
公开(公告)日：2013-09-17
申请号：KR1020120023599
申请日：2012-03-07
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/00 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1675 , H01L45/1683 , H01L27/2481
Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to improve crystallization by performing an active epitaxial growth process on the front surface of a substrate. CONSTITUTION: A first semiconductor layer (118) has a first conductivity type. The first semiconductor layer is extended in a first direction. Second semiconductor layers (122) are separated from each other in the first direction. The second semiconductor layer has a second conductivity type. An insulating layer structure (130) surrounds the sidewalls of the first semiconductor layer and the second semiconductor layers and.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过在衬底的前表面上进行有源外延生长工艺来改善结晶。 构成：第一半导体层（118）具有第一导电类型。 第一半导体层沿第一方向延伸。 第二半导体层（122）在第一方向上彼此分离。 第二半导体层具有第二导电类型。 绝缘层结构（130）围绕第一半导体层和第二半导体层的侧壁。
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公开(公告)号：KR1020120097963A
公开(公告)日：2012-09-05
申请号：KR1020110017565
申请日：2011-02-28
Applicant: 삼성전자주식회사
CPC classification number: G06F21/00 , G06F11/1012 , G06F11/108 , G06F12/00 , G06F12/14 , G11C11/00 , G11C11/5642 , G11C16/26 , G11C16/3418
Abstract: PURPOSE: A nonvolatile memory device, a controller for controlling the same, and a controller operating method are provided to improve the data reliability of a nonvolatile memory by the operation of a memory controller. CONSTITUTION: A voltage generating circuit generates a hard decision read voltage and a soft decision read voltage. A random sequence generating circuit(50) generates a random sequence. A page buffer(35) is connected to a memory cell array through a bit line and includes a latch which stores hard decision data and soft decision data. A multiplexer circuit selectively transmits program data and the random sequence to the page buffer. A control logic unit(31) controls the random sequence generating circuit, the page buffer, and the multiplexer circuit.
Abstract translation: 目的：提供一种非易失性存储器件，用于控制其的控制器和控制器操作方法，以通过存储器控制器的操作来提高非易失性存储器的数据可靠性。 构成：电压发生电路产生硬判决读取电压和软判定读取电压。 随机序列生成电路（50）生成随机序列。 页缓冲器（35）通过位线连接到存储单元阵列，并且包括存储硬判决数据和软判决数据的锁存器。 多路复用器电路选择性地将程序数据和随机序列发送到页缓冲器。 控制逻辑单元（31）控制随机序列产生电路，寻呼缓冲器和多路复用器电路。
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公开(公告)号：KR1020120030817A
公开(公告)日：2012-03-29
申请号：KR1020100092586
申请日：2010-09-20
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C16/0483 , H01L27/1157 , H01L27/11582 , G11C16/08 , G11C11/5628 , G11C16/32 , G11C29/42
Abstract: PURPOSE: A flash memory system and a word line interleaving method thereof are provided to alleviate an imbalance of bit error rate between different word lines using a word line interleaving operation. CONSTITUTION: A memory cell array is connected to a plurality of word lines. A word line(WL) interleaving logic(1230) performs an WL interleaving operation with respect to WL data corresponding to the word lines. The WL interleaving logic arranges the mixed WL data to the memory cell array. An error correction code circuit(1240) generates a parity bit of an error correction code from the WL data before performing the WL interleaving operation.
Abstract translation: 目的：提供闪存系统及其字线交错方法，以减轻使用字线交错操作的不同字线之间误码率的不平衡。 构成：存储单元阵列连接到多个字线。 字线（WL）交织逻辑（1230）对与字线对应的WL数据执行WL交错操作。 WL交错逻辑将混合WL数据布置到存储单元阵列。 纠错码电路（1240）在执行WL交错操作之前，从WL数据生成纠错码的奇偶校验位。
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44.发明公开불휘발성 메모리 장치의 동작 방법, 컨트롤러의 동작 방법, 그리고 불휘발성 메모리 장치 및 컨트롤러를 포함하는 메모리 시스템의 동작 방법 无效非易失性存储器件的操作方法，控制器的操作方法和包括非易失性存储器件和控制器的存储器系统的操作方法
公开(公告)号：KR1020110100739A
公开(公告)日：2011-09-15
申请号：KR1020100019730
申请日：2010-03-05
Applicant: 삼성전자주식회사
IPC: G06F12/04
Abstract: 본 발명은 불휘발성 메모리 장치 및 컨트롤러를 포함하는 메모리 시스템의 동작 방법에 관한 것이다. 본 발명의 메모리 시스템의 동작 방법은 소스 워드를 수신하고, 수신된 소스 워드를 코드 워드로 변환하고, 그리고 변환된 코드 워드를 불휘발성 메모리 장치에 프로그램하는 것으로 구성된다. 변환된 코드 워드의 길이는 수신된 소스 워드의 길이보다 길다. 변환된 코드 워드의 제 1 디지털 비트들의 수 및 제 2 디지털 비트들의 수의 차이는 기준값보다 작다.
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公开(公告)号：KR1020110099566A
公开(公告)日：2011-09-08
申请号：KR1020100018660
申请日：2010-03-02
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3427 , G11C16/26
Abstract: 본 발명은 메모리 시스템 및 그것의 동작 방법에 관한 것이다. 본 발명에 의하면,불휘발성 메모리 장치를 포함하는 메모리 시스템이 동작하는 방법은 읽기 전압을 달리하여 관찰 메모리 셀을 적어도 1번 읽어 제 1 읽기 데이터 심볼을 형성하는 단계, 읽기 전압을 달리하여 상기 관찰 메모리 셀에 인접한 간섭 메모리 셀들을 적어도 1번 읽어 제 2 읽기 데이터 심볼들을 형성하는 단계, 및 상기 제 1 읽기 데이터 심볼과 상기 제 2 읽기 데이터 심볼들에 기반하여, 상기 관찰 메모리 셀의 논리값을 판별하는 단계로 구성된다.
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Patent Agency Ranking
公开(公告)号：KR1020100120991A
公开(公告)日：2010-11-17
申请号：KR1020090039906
申请日：2009-05-07
Applicant: 삼성전자주식회사
CPC classification number: H03M13/455 , G06F11/1068 , G11C16/26
Abstract: PURPOSE: A memory system performing easer manipulation and a reading method thereof are provided to select eraser by repeating the reading operation in the same voltage level when error correction is impossible, thereby correcting the error by the eraser. CONSTITUTION: A memory controller reads a data from a memory in a reference voltage level(VR)(S110). If the error correction of data is impossible, an error correction circuit corrects an error of the data(S120,S125). Otherwise, the erasure decoding of the data is determined(S130). The eraser manipulator selects erasure candidates by repeating the reading operation in a reference voltage level(S140). A erasure manipulator manipulates eraser by the selected erasure candidates(S150).
Abstract translation: 目的：提供执行简易操作的记忆系统及其读取方法，以便在不可能进行纠错的情况下通过重复相同电压电平的读取操作来选择橡皮擦，从而通过橡皮擦校正错误。 构成：存储器控制器以参考电压电平（VR）从存储器读取数据（S110）。 如果数据的纠错不可能，则纠错电路校正数据的错误（S120，S125）。 否则，确定数据的擦除解码（S130）。 橡皮擦操纵器通过重复参考电压电平中的读取操作来选择擦除候选（S140）。 擦除机械手通过选择的擦除候选来操纵橡皮擦（S150）。
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公开(公告)号：KR1020100106142A
公开(公告)日：2010-10-01
申请号：KR1020090024628
申请日：2009-03-23
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1006 , G11C7/1042 , G11C8/10 , G11C11/5628 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2211/5623
Abstract: PURPOSE: A nonvolatile memory device and a memory system including the same are provided to perform an interleaving program and deinterleaving reading by storing program data according the reading period and writing period of the nonvolatile memory device. CONSTITUTION: A memory cell array(210) is connected to read/write circuit(230) through a bit line(BL). An address decoder(220) is connected to the memory cell array through a word line(WL). A reading/ writing circuit is connected to the storing circuit(240) through the data line(DL). The storing circuit is connected to the reading/ writing circuit through the data lines. The storing circuit operates in response to the control of a control logic(250).
Abstract translation: 目的：提供一种非易失性存储器件和包括该非易失性存储器件的存储器系统，以通过根据非易失性存储器件的读取周期和写入周期存储程序数据来执行交织程序和解交错读取。 构成：存储单元阵列（210）通过位线（BL）连接到读/写电路（230）。 地址解码器（220）通过字线（WL）连接到存储单元阵列。 读/写电路通过数据线（DL）连接到存储电路（240）。 存储电路通过数据线连接到读/写电路。 存储电路响应于控制逻辑（250）的控制而工作。
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公开(公告)号：KR1020100104623A
公开(公告)日：2010-09-29
申请号：KR1020090023167
申请日：2009-03-18
Applicant: 삼성전자주식회사
CPC classification number: H03M13/618 , G06F11/1012 , H03M13/13 , H03M13/353 , H03M13/3738 , H03M13/6356 , H03M13/6362
Abstract: PURPOSE: A data processing system and a code rate control scheme thereof are provided to optimize the overhead of error control coding by varying the code rate of single ECC(Error Correction Code) codec according to the property of a channel, thereby improving the reliability of a data processing system. CONSTITUTION: A data processing system comprises a memory(1000), an encoding and decoding block(2500), and a code rate control block(2600). The memory has a plurality of storage areas. The encoding and decoding block decodes the data read from an accessed storage area according to the fixed code rate. The code rate control block has code rates corresponding to the respective storage areas. The code rate control block changes the code rate corresponding to the accessed storage area which is determined by the data read from the accessed storage area and the data decoded by the encoding and decoding block.
Abstract translation: 目的：提供一种数据处理系统及其码率控制方案，以通过根据信道的性质改变单个ECC（纠错码）编解码器的码率来优化错误控制编码的开销，从而提高信道的可靠性 一个数据处理系统。 构成：数据处理系统包括存储器（1000），编码和解码块（2500）和码率控制块（2600）。 存储器具有多个存储区域。 编码和解码块根据固定码率对从访问的存储区域读取的数据进行解码。 码率控制块具有对应于相应存储区域的码率。 码率控制块改变由从所访问的存储区域读取的数据和由编码和解码块解码的数据确定的访问存储区域的码率。
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公开(公告)号：KR1020100090966A
公开(公告)日：2010-08-18
申请号：KR1020090010219
申请日：2009-02-09
Applicant: 삼성전자주식회사
CPC classification number: G11C13/00 , G11C7/1006 , G11C11/5628 , G11C13/0033 , G11C16/3427 , G11C29/00
Abstract: PURPOSE: A semiconductor memory device and a data processing method thereof are provided to improve the reliability of data by programming the state of memory cells to avoid an arrangement which causes an error. CONSTITUTION: Data to be programmed in the row and column of a nonvolatile memory is arranged according to row and column directions. The data is coded to a modulation code according to the row or column directions. A modulation coding unit(110) codes program data from a host with a modulation coding method and transmits the coded program to a nonvolatile memory device(120). The modulation coding unit decodes the read data outputted from the nonvolatile memory device and transmits the decoded data to the host. The nonvolatile memory device writes the program data supplied from the modulation coding unit on the nonvolatile memory cells of a cell array(121). The coded program data is simultaneously loaded on a page buffer(122) of the nonvolatile memory device.
Abstract translation: 目的：提供一种半导体存储器件及其数据处理方法，通过对存储器单元的状态进行编程以避免导致错误的布置来提高数据的可靠性。 构成：根据行和列方向布置要在非易失性存储器的行和列中编程的数据。 根据行或列方向将数据编码为调制码。 调制编码单元（110）使用调制编码方法对来自主机的节目数据进行编码，并将编码的节目发送到非易失性存储装置（120）。 调制编码单元对从非易失性存储器件输出的读取数据进行解码，并将解码的数据发送到主机。 非易失性存储器件将从调制编码单元提供的程序数据写入单元阵列（121）的非易失性存储单元。 编码程序数据被同时加载在非易失性存储器件的页缓冲器（122）上。
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公开(公告)号：KR1020090099757A
公开(公告)日：2009-09-23
申请号：KR1020080024930
申请日：2008-03-18
Applicant: 삼성전자주식회사
IPC: G11C29/42
CPC classification number: H03M13/2903 , G06F11/1072 , H03M13/29 , H03M13/353
Abstract: PURPOSE: A memory device and an encoding/decoding method are provided to improve error correctability and to reduce an error ratio of a critical data page. CONSTITUTION: A memory device includes a memory cell array, an internal decoder, and an external decoder(340). The internal decoder ECC(Error Control Codes) decodes a first code word(311) by applying a first decoding method selected based on the characteristic of a first channel to the first code word read from the memory cell array. The internal decoder ECC decodes a second code word(321) by applying a second decoding method selected based on the characteristic of the second channel to the second code word read from the memory cell array. The external decoder ECC decodes the ECC decoded first code word and the ECC decoded second code word by applying the external decoding method.
Abstract translation: 目的：提供存储器件和编码/解码方法，以提高错误校正能力并降低关键数据页的错误率。 构成：存储器件包括存储单元阵列，内部解码器和外部解码器（340）。 内部解码器ECC（错误控制代码）通过将从第一通道的特性选择的第一解码方法应用于从存储单元阵列读取的第一代码字来解码第一代码字（311）。 内部解码器ECC通过将从第二通道的特性选择的第二解码方法应用于从存储单元阵列读取的第二代码字来对第二代码字（321）进行解码。 外部解码器ECC通过应用外部解码方法对ECC解码的第一码字和ECC解码的第二码字进行解码。
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