公开(公告)号：KR1020130047715A

公开(公告)日：2013-05-08

申请号：KR1020130039522

申请日：2013-04-10

Applicant: 서울대학교산학협력단

Inventor： 황철성 ,  석준영

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/0688 ,  H01L45/06 ,  H01L45/085 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

Abstract: PURPOSE: A 3D non-volatile memory device and a method for fabricating the same are provided to define a memory cell by intersecting a flat-type conductive plate with a line-type conductive line, and to secure a cross bar-type 3D array structure. CONSTITUTION: Conductive lines(BL11,BL12,BL13,BL21,BL22,BL23) which are parallelly separated from each other are formed. Conductive plates(WP1,WP2,WP3) which are parallelly separated from each other and intersects the conductive lines are formed. The conductive lines and the conductive plates define cross points in the X, the Y, and the Z direction. A nonvolatile information storage layer pattern(SM) for storing a bit value between the cross points is formed. The nonvolatile information storage layer pattern arranged in the cross points defines a unit memory cell.

Abstract translation: 目的：提供一种3D非易失性存储器件及其制造方法，以通过将平面型导电板与线型导电线相交而限定存储器单元，并且固定横杆型3D阵列结构 。 构成：形成彼此平行分离的导电线（BL11，BL12，BL13，BL21，BL22，BL23）。 形成彼此平行分离并与导电线相交的导电板（WP1，WP2，WP3）。 导线和导电板在X，Y和Z方向上限定交叉点。 形成用于存储交叉点之间的位值的非易失性信息存储层图案（SM）。 布置在交叉点中的非易失性信息存储层图案限定单位存储单元。

公开(公告)号：KR1020130011550A

公开(公告)日：2013-01-30

申请号：KR1020110072779

申请日：2011-07-22

Applicant: 서울대학교산학협력단

Inventor： 황철성 ,  엄태용

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144

Abstract: PURPOSE: A phase change memory device and a manufacturing method thereof are provided to form a high density phase change memory film and to prevent the deterioration of the phase change memory film. CONSTITUTION: An interlayer insulating film(20) including a contact hole is formed on a substrate. A phase change material layer(30a) and a buffer layer(30b) are alternatively formed on the inter layer insulating film to fill the contact hole of the inter layer insulating film. The contact interface between the buffer layer and the phase change material layer are formed in the laminated structure. The laminated structure is heat-treated to reflow the phase change material layer in the contact hole.

Abstract translation: 目的：提供相变存储器件及其制造方法以形成高密度相变存储膜并防止相变存储膜的劣化。 构成：在基板上形成包括接触孔的层间绝缘膜（20）。 交替地在层间绝缘膜上形成相变材料层（30a）和缓冲层（30b），以填充层间绝缘膜的接触孔。 缓冲层和相变材料层之间的接触界面形成在层叠结构中。 对层叠结构进行热处理以使接触孔中的相变材料层回流。

公开(公告)号：KR101079662B1

公开(公告)日：2011-11-03

申请号：KR1020090050426

申请日：2009-06-08

Applicant: 서울대학교산학협력단

Inventor： 황철성 ,  석준영

IPC: H01L21/8247 ,  G11C13/02 ,  H01L27/115

Abstract: 본발명은정보기록및 판독시에오기와오독의우려가발생하지않는저항변화랜덤액세스메모리및 저항변화랜덤액세스메모리의정보기록방법과판독방법에관한것이다. 본발명에따른저항변화랜덤액세스메모리는 m×n(m, n은 2 이상의자연수) 매트릭스(matrix)를이루도록 m×n 개의불순물영역이형성되어있고, 행방향의불순물영역각각의사이에채널영역이형성되어, 각행 방향으로비트라인이형성되어있는기판을구비한다. 그리고각 채널영역상에순차적으로적층되어있는게이트절연막과게이트전극을구비한다. 그리고각 게이트전극상에형성되며게이트전극과전기적으로연결되는연결전극과, 연결전극상에행 방향으로길게뻗은형상으로형성되며각 행에배치된연결전극을전기적으로연결시키는게이트라인을구비한다. 그리고각 불순물영역상에순차적으로적층되어있는각 불순물영역과전기적으로연결되는하부전극과, 전기신호에의해저항이변화하는물질로이루어진저항변화층과, 각저항변화층상에형성된상부전극을구비한다. 그리고상부전극상에열 방향으로길게뻗은형상으로형성되며, 각열에배치된상부전극을전기적으로연결시키는워드라인을구비한다.

公开(公告)号：KR101075077B1

公开(公告)日：2011-10-19

申请号：KR1020090116923

申请日：2009-11-30

Applicant: 서울대학교산학협력단

Inventor： 황철성

IPC: H01L27/115 ,  H01L21/8247

Abstract: 본발명은집적도를증가시키기위해수직방향으로적층가능한낸드플래시메모리소자에관한것이다. 본발명에따른낸드플래시메모리소자는기판과, 기판상에형성된산화물반도체채널과, 산화물반도체채널상에순차적으로적층되어형성된터널링절연막, 플로팅게이트, 블로킹절연막및 콘트롤게이트과, 산화물반도체채널의양측에형성되어있는소스와드레인을구비한다.

公开(公告)号：KR1020110060361A

公开(公告)日：2011-06-08

申请号：KR1020090116923

申请日：2009-11-30

Applicant: 서울대학교산학협력단

Inventor： 황철성

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  G11C16/10 ,  H01L21/28273

Abstract: PURPOSE: A NAND flash memory device with an oxide semiconductor channel is provided to increase integration by vertically stacking devices. CONSTITUTION: A substrate is made of insulation materials. An oxide semiconductor channel(120) is formed on a substrate. A tunneling insulation layer(150), a floating gate, a blocking insulation layer, and a control gate are successively laminated on the oxide semiconductor channel. A source and a drain(130) are formed on both sides of the It is formed in both sides of the oxide semiconducting channel and are made of the same materials as the oxide semiconductor channel.

Abstract translation: 目的：提供具有氧化物半导体通道的NAND快闪存储器件，以通过垂直堆叠器件增加集成度。 构成：基材由绝缘材料制成。 在衬底上形成氧化物半导体沟道（120）。 隧道绝缘层（150），浮栅，隔离绝缘层和控制栅极依次层叠在氧化物半导体沟道上。 源极和漏极（130）形成在其两侧，其形成在氧化物半导体沟道的两侧，并且由与氧化物半导体沟道相同的材料制成。

公开(公告)号：KR1020110049182A

公开(公告)日：2011-05-12

申请号：KR1020090106081

申请日：2009-11-04

Applicant: 서울대학교산학협력단

Inventor： 황철성 ,  최설 ,  엄태용

IPC: H01L21/3065 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/3065 ,  C23C16/305 ,  H01L45/141 ,  H01L45/144

Abstract: PURPOSE: A method for etching a chalcogenide thin film and method for cleaning a chalcogenide thin film depositing device are provided to easily etch a chalcogenide thin film using NH3 plasma. CONSTITUTION: A chalcogenide thin film is formed on a substrate to form a lamination structure. A chalcogenide thin film is etched by supplying NH3 plasma to the chalcogenide thin film. The chalcogenide thin film is etched at a temperature which is above 180°C. The chalcogenide thin film is deposited using a chalcogenide thin film depositing device. The inside of the chalcogenide thin film depositing device is cleaned by supplying NH3 plasma to the chalcogenide thin film depositing device.

Abstract translation: 目的：蚀刻硫族化物薄膜的方法和清洗硫族化物薄膜沉积装置的方法是为了使用NH 3等离子体容易地蚀刻硫族化物薄膜。 构成：在基板上形成硫族化物薄膜以形成层压结构。 通过向硫族化物薄膜提供NH 3等离子体来蚀刻硫族化物薄膜。 在高于180℃的温度下蚀刻硫族化物薄膜。 使用硫族化物薄膜沉积装置沉积硫族化物薄膜。 硫属化物薄膜沉积装置的内部通过向硫族化物薄膜沉积装置提供NH 3等离子体来清洗。

公开(公告)号：KR101003451B1

公开(公告)日：2010-12-28

申请号：KR1020090065764

申请日：2009-07-20

Applicant: 서울대학교산학협력단

Inventor： 황철성

IPC: H01L27/115

CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L21/28202 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792 ,  H01L45/141

Abstract: PURPOSE: A charge trap flash memory device with a GST nano dot is provided to improve the device property by increasing the trapped charge quantity and increasing trap density. CONSTITUTION: A semiconductor substrate(110) includes a source region and a drain region separated by a channel region. A tunneling insulating layer is formed on the channel region of the semiconductor substrate. A chalcogenide based compound nano dot is formed on the tunneling insulation layer. A blocking insulation layer(140) is formed on the tunneling insulation layer to cover the chalcogenide based compound nano dot.

Abstract translation: 目的：提供具有GST纳米点的电荷陷阱闪存器件，以通过增加捕获的电荷量和增加陷阱密度来提高器件性能。 构成：半导体衬底（110）包括由沟道区域分离的源极区域和漏极区域。 隧道绝缘层形成在半导体衬底的沟道区上。 在隧道绝缘层上形成硫属元素化合物纳米点。 在隧道绝缘层上形成阻挡绝缘层（140）以覆盖基于硫族化物的复合纳米点。

公开(公告)号：KR1020090009455A

公开(公告)日：2009-01-23

申请号：KR1020070072742

申请日：2007-07-20

Applicant: 에스케이하이닉스 주식회사 ,  서울대학교산학협력단

Inventor： 박남균 ,  박해찬 ,  황철성 ,  최병준

IPC: H01L27/115

CPC classification number: H01L45/144 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1675 ,  H01L45/1683 ,  H01L45/143

Abstract: A phase change memory device is provided to form a buffer layer for reinforcing interfacial bonding in an interface between a phase changing film and an insulating layer, thereby suppressing delamination of the phase changing film caused by unstable bonding between the phase changing film and the insulating layer. A bottom electrode(310) is formed in each phase change cell domain of a semiconductor substrate(300) having a plurality of phase change cell domains. An insulating layer(320) is evaporated on the semiconductor substrate in order to cover the bottom electrode. A contact hole exposing the bottom electrode is formed by etching the insulating layer. A contact plug(330) contacting the bottom electrode is formed within the contact hole. A buffer layer(340) is formed on the insulating layer including the contact plug. The buffer layer is formed with one of a tiO2 film, a la2O3 film, an hfO2 film, a ta2O5 film, a zrO2 film and an Y2O3 film. Phase change material(350) and a conductive film(360) for an upper electrode are successively evaporated on the buffer layer. The buffer layer has excellent property for adhesive with the phase change material. The phase change material is formed on the buffer film in a form of a thin film comprising elaborate grains.

Abstract translation: 提供相变存储器件以形成用于加强相变膜和绝缘层之间的界面中的界面结合的缓冲层，从而抑制由相变膜和绝缘层之间的不稳定接合引起的相变膜的分层 。 在具有多个相变元件区域的半导体衬底（300）的每个相变单元区域中形成底部电极（310）。 在半导体衬底上蒸发绝缘层（320）以覆盖底部电极。 通过蚀刻绝缘层形成露出底部电极的接触孔。 在接触孔内形成接触底部电极的接触插塞（330）。 在包括接触插塞的绝缘层上形成缓冲层（340）。 缓冲层由TiO 2膜，1a2O3膜，hfO2膜，ta2O5膜，zrO2膜和Y2O3膜中的一种形成。 在缓冲层上依次蒸发用于上电极的相变材料（350）和导电膜（360）。 缓冲层对于具有相变材料的粘合剂具有优异的性能。 相变材料形成在缓冲膜上，其形式为包含精细晶粒的薄膜。

公开(公告)号：KR101935608B1

公开(公告)日：2019-01-04

申请号：KR1020120033879

申请日：2012-04-02

Applicant: 서울대학교산학협력단

Inventor： 황철성 ,  박민혁

IPC: H01L27/115 ,  H01L21/8247

公开(公告)号：KR101748949B1

公开(公告)日：2017-06-21

申请号：KR1020150132080

申请日：2015-09-18

Applicant: 서울대학교산학협력단

Inventor： 황철성

IPC: H01L27/108 ,  H01L21/31

CPC classification number: H01L27/10808 ,  H01L27/10855

Abstract: 본발명의실시예들은커패시터를포함하는반도체메모리소자및 이의제조방법에관한것이다. 일실시예에따른반도체메모리소자의상기커패시터는, 스위칭소자에전기적으로연결되어기판의상부표면에노출되고, 상기기판에평행한제 1 방향및 상기제 1 방향과다른제 2 방향으로배열복수의콘택들; 상기기판상에서상기복수의콘택들중 상기제 1 방향으로인접하는콘택들사이에형성되고, 소정의두께를갖고상기제 2 방향으로소정의폭을갖도록형성되며, 상기기판의수직방향으로신장된몰드절연체들; 상기몰드절연체들각각의제 1 방향에수직하는측벽상에제공되어지지되고상기복수의콘택들에각각전기적으로연결되는수직평판구조의하부전극들; 상기하부전극들상에형성되는유전막; 및상기유전막상에형성되는상부전극을포함한다.

Abstract translation: 本发明的实施例涉及包括电容器的半导体存储器件及其制造方法。 根据实施例的半导体存储器件的电容器电连接到开关元件并且暴露在基板的上表面上，并且布置在平行于基板的第一方向上并且在不同于第一方向的第二方向上 联系人; 在基板上的多个接触件的第一方向上的接触件之间形成有多个接触件，该多个接触件在第二方向上具有预定的厚度和预定的宽度， 的绝缘体; 竖直板结构的下电极，所述竖直板结构的下电极支撑在并且支撑在垂直于每个所述模制绝缘体的第一方向的侧壁上并且分别电连接到所述多个触点; 形成在下电极上的介电层; 并且在电介质膜上形成上部电极。