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公开(公告)号：KR1020100073035A
公开(公告)日：2010-07-01
申请号：KR1020080131613
申请日：2008-12-22
Applicant: 한국전자통신연구원
CPC classification number: H03F3/45475 , H03F3/45968 , H03F2203/45212
Abstract: PURPOSE: A high speed multi-voltage comparator is provided to reduce the output recovery time by resetting the output of each pre-amplifier with a reset switch. CONSTITUTION: A multi-stage amplifier is formed by interlinking a plurality of pre-amplifiers(A21-A23) as multi-stage. A latch(L) is connected to an output terminal of the multi-stage amplifier. A plurality of capacitors(C1-C6) stores voltages outputted from pre-amplifiers. A plurality of offset removal switches is connected to the output terminals of pre-amplifiers. The offset removal switches removes offset in the outputs of pre-amplifiers. A plurality of reset switches is connected to the output terminals of pre-amplifiers. The reset switches reset the outputs of pre-amplifiers. Offset removal switches and reset switches connected to the output terminals of pre-amplifiers act in response to the clock which each other does not put one upon another.
Abstract translation: 目的：提供高速多电压比较器，通过复位开关复位每个前置放大器的输出来减少输出恢复时间。 构成：通过将多个前置放大器（A21-A23）互连为多级而形成多级放大器。 锁存器（L）连接到多级放大器的输出端子。 多个电容器（C1-C6）存储从前置放大器输出的电压。 多个偏移去除开关连接到前置放大器的输出端子。 偏移去除开关消除前置放大器输出端的偏移。 多个复位开关连接到前置放大器的输出端子。 复位开关复位前置放大器的输出。 连接到前置放大器的输出端子的偏移去除开关和复位开关响应于彼此不彼此放置的时钟而起作用。
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公开(公告)号：KR1020100038755A
公开(公告)日：2010-04-15
申请号：KR1020080097842
申请日：2008-10-06
Applicant: 한국전자통신연구원
CPC classification number: H03M1/162
Abstract: PURPOSE: According to the resolution which the algorithm A-D converter is required, the power consumption of the algorithm ADC(Analog to Digital Converter) is minimized by dynamically reducing the bandwidth of the operational amplifier included in MDAC(Multiplying Digital-to-Analog Converter). CONSTITUTION: A flash a DC(310) is composed of the structure of holding in common the preprocessing amplifier. The flash a DC changes the analog input signal into the digital signal. The MDAC(350) is composed of the first and the second digital-to-analog C, and subtract and operational amplifier. MDAC again changes the residual voltage transformed in the flash a DC into the analog signal, the bandwidth control signal generator(360) outputs the bandwidth control signal which becomes according to the required resolution to the operational amplifier of MDAC.
Abstract translation: 目的：根据需要算法AD转换器的分辨率，通过动态降低包含在MDAC（乘法数模转换器）中的运算放大器的带宽，算法ADC（模数转换器）的功耗最小化， 。 构成：闪光灯DC（310）由保持预处理放大器的结构组成。 闪光灯一个DC将模拟输入信号改变成数字信号。 MDAC（350）由第一和第二数字模拟C和减法运算放大器组成。 MDAC再次将闪速DC变换的残余电压改变为模拟信号，带宽控制信号发生器（360）将根据所需分辨率变化的带宽控制信号输出到MDAC的运算放大器。
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公开(公告)号：KR1020090038679A
公开(公告)日：2009-04-21
申请号：KR1020070104108
申请日：2007-10-16
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1225 , H03M1/167
Abstract: An apparatus and a method for algorithmic digital analog converting are provided to reduce the electricity of being used in the algorithmic digital-to-analog changing apparatus. An algorithmic digital to analog converter comprises an SHA(101), an MDAC(Multiplying Digital Analog Converter)(103), the first, second, and third flash ADCs(105,107,109) and a digital correction circuit(111). The SHA samples the analog signal received from the outside and holds and outputs. The MDAC calculates the difference of the analog signal of the former step and the digital signal of the current step, and delivers the to the next step. The first, second and third flash ADCs convert the analog signal outputted from the MDAC into the digital signal and output the first digital signal to the MDAC. The digital correction circuit corrects the signal outputted from the flash ADC and outputs the digital signal of the overlapped n-bit.
Abstract translation: 提供了一种用于算法数字模拟转换的装置和方法，以减少在算法数模转换装置中使用的电能。 算法数模转换器包括SHA（101），MDAC（乘法数字模拟转换器）（103），第一，第二和第三闪存ADC（105,107,109）和数字校正电路（111）。 SHA对从外部接收的模拟信号进行采样并保持和输出。 MDAC计算前一步骤的模拟信号与当前步骤的数字信号的差异，并传送到下一步。 第一，第二和第三闪存ADC将从MDAC输出的模拟信号转换为数字信号，并将第一数字信号输出到MDAC。 数字校正电路校正从闪存ADC输出的信号，并输出重叠n位的数字信号。
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