公开(公告)号：WO1994014121A1

公开(公告)日：1994-06-23

申请号：PCT/US1993011847

申请日：1993-12-06

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  WOOTEN, David, R. ,  MILLER, Craig, A. ,  LEIGH, Kevin, B. ,  COSTLEY, Robert, Brett ,  SIMONICH, Christopher, E.

IPC: G06F13/40

CPC classification number: G06F13/4022

Abstract: A point to point connection architecture for a computer I/O subsystem, resulting in a scalable tree structure. A Master I/O Concentrator (MIOC) is connected to the host bus and handles conversion between a bus oriented structure and the tree structure of the I/O subsystem. Ports away from the host bus are downstream ports and conform to a simple byt wide message protocol. Various IOCs and devices can be attached to one of the downstream ports on the MIOC. The MIOC directs transmissions to the appropriate channel based on a geographical addressing scheme. The IOC connections act as further points of branching. Ultimately IOD or I/O devices are reached, having an upstream port for connection to the IOC and a downstream port and internal logic appropriate for the particular peripheral device. Various registers are present in the IOCs and the IODs to allow determination of the topology and particular devices present. Messages and commands are transfered in the I/O subsystem in defined packets. Various read, write and exchange commands are used, with a read response being utilized to allow split transaction read operations. Certain status and control commands are also present. Interrupts are handled by having the interrupt levels correspond to memory addresses of the programmable interrupt controller, thus allowing simple selection of interrupts to be generated by the devices and no need for separate wiring.

Abstract translation: 用于计算机I / O子系统的点对点连接架构，从而产生可扩展的树结构。 主I / O集中器（MIOC）连接到主机总线，处理面向总线的结构与I / O子系统的树结构之间的转换。 远离主机总线的端口是下游端口，并符合简单的直接宽信息协议。 各种IOC和设备可以连接到MIOC的下游端口之一。 MIOC根据地理寻址方案将传输指向适当的信道。 IOC连接充当分支的进一步点。 最终到达IOD或I / O设备，具有连接到IOC的上行端口和下游端口以及适用于特定外围设备的内部逻辑。 各种寄存器存在于IOC和IOD中，以允许确定拓扑和存在的特定设备。 消息和命令在定义的数据包中在I / O子系统中传输。 使用各种读取，写入和交换命令，其中使用读取响应来允许拆分事务读取操作。 还存在某些状态和控制命令。 中断通过使中断电平对应于可编程中断控制器的存储器地址来处理，从而允许简单地选择要由器件产生的中断，而不需要单独的布线。

公开(公告)号：WO1994011999A3

公开(公告)日：1994-05-26

申请号：PCT/US1993010984

申请日：1993-11-08

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  DYKES, Don, A. ,  CASTELL, Robin, T. ,  CLARK, Andrew, C. ,  NAGEL, Paul, E. ,  TRAN, Huyen, B. ,  JONES, Randall, L. ,  BALDRIDGE, Ronald, L.

IPC: H04Q07/04

公开(公告)号：WO1994009436A1

公开(公告)日：1994-04-28

申请号：PCT/US1993009784

申请日：1993-10-04

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  CALLISON, Ryan, A. ,  CHANDLER, Gregory, T. ,  GRIEFF, Thomas, W.

IPC: G06F13/12

CPC classification number: G06F3/0601 ,  G06F12/0866 ,  G06F13/124 ,  G06F2003/0692

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.

Abstract translation: 一种磁盘阵列控制器板，其使用作为其内部数据总线上的从机的EISA总线主机，以允许先进的驱动器阵列控制器芯片（ADAC）作为主机操作。 ADAC连接到传输缓冲RAM。 内部数据总线的协议提供了将主机存储器地址加载到总线从站中的周期，以提供传输计数信息和从属特定信息以及一系列数据传输周期。 本地处理器连接到EISA总线主控和ADAC控制操作并提供某些信息。 ADAC由称为命令描述符块（CDB）的结构控制。 每个CDB包括描述ADAC用于执行其传送操作的各种地址，控制位和功能位的信息。 本地处理器直接将形成CDB的数据写入并存储到传送缓冲器RAM中。 ADAC获得CDB，将数据加载到寄存器中，然后根据这些寄存器中包含的信息执行操作，直到传输完成。 ADAC本身执行操作，包括自动条纹散射和收集，以从条形阵列数据开发连续的主机内存字段。 一系列CDB可以链接，以便可以开发一系列复杂的任务。 在一个变化中，开发了一串CDB来传输数据，但是一些数据被传送到比特桶，而其他数据被实际传输。

公开(公告)号：WO1994008306A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009364

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  GALLOWAY, William, C.

IPC: G06F13/42

CPC classification number: G06F13/4226

Abstract: An SCSI device resides and communicates on the SCSI bus without that device being assigned an SCSI address or corresponding SCSI ID. The driver software on the host computer directs the SCSI initiator device to select itself as its target, so the initiator then only asserts one bit of the eight bit SCSI data bus. The SCSI device determines when a SELECTION phase is under way and then determines if only one bit has been asserted on the SCSI data bus. The SCSI device then responds to the initiator as being the target device, thus completing the SELECTION phase. The initiator and the SCSI device can then communicate as a normal initiator and target would during information transfer stages of the SCSI standard. This is all done without the SCSI device occupying a normal SCSI address.

Abstract translation: SCSI设备驻留并在SCSI总线上进行通信，而不会为该设备分配SCSI地址或相应的SCSI ID。 主机上的驱动程序软件指示SCSI启动器设备将其自身选为其目标，因此启动器只会断言8位SCSI数据总线的一位。 SCSI设备确定SELECTION阶段何时正在进行，然后确定SCSI数据总线上是否只有一个位被置位。 然后，SCSI设备作为目标设备响应发起者，从而完成SELECTION阶段。 然后，启动器和SCSI设备可以在SCSI标准的信息传输阶段中作为正常启动器和目标进行通信。 没有SCSI设备占用正常的SCSI地址就完成了。

公开(公告)号：WO1994008303A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009430

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  FRY, Walter, G. ,  WOLFORD, Jeff, W.

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F12/0831

Abstract: A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.

Abstract translation: 一种在某些操作期间减少高速缓存控制器的非窥探窗口以增加主机总线效率的方法和装置。 高速缓存控制器需要总线授权信号来执行周期，并且在提供总线授权信号直到循环完成之后才能窥探周期。 缓存接口逻辑监控缓存控制器的周期，这些周期需要扩展总线或本地I / O总线。 当检测到这样的周期时，设备开始周期，并且不向总线授权信号断言到高速缓存控制器。 因此，高速缓存控制器认为该周期尚未开始，因此能够执行其他操作，例如窥探其他主机总线周期。 在此期间，循环执行。 当读取数据返回或写数据到达其目的地时，接口逻辑在适当的时间向缓存控制器提供总线授权周期。 通过以这种方式延迟总线授权信号，减少非窥视窗口。

公开(公告)号：WO1994006570A1

公开(公告)日：1994-03-31

申请号：PCT/US1993008396

申请日：1993-09-03

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  HAYES, Donald, J.

IPC: B05D01/00

CPC classification number: B05C11/08 ,  B05D1/005 ,  Y10T428/24777 ,  Y10T428/24793 ,  Y10T428/24802 ,  Y10T428/265 ,  Y10T428/31504

Abstract: A method for film coated passivation of individual grooves or channels in an array of closely spaced grooves or channels of a workpiece, for example, ink channels in a printhead employed in an ink jet printer device; includes the steps of placing the workpiece on a rotation plate having a rotational center, securing the workpiece to the rotation plate with the grooves directed radially outward from the rotational center of the rotation plate, placing resin upon the workpiece in the vicinity of the grooves, and spinning the rotation plate to cause the resin to migrate along the surfaces of the grooves and thereby coating them.

Abstract translation: 用于在喷墨打印机装置中使用的打印头中的油墨通道的工件的紧密间隔的凹槽或通道的阵列中的单个凹槽或通道的薄膜涂覆钝化的方法; 包括将工件放置在具有旋转中心的旋转板上的步骤，将工件固定到旋转板上，其中凹槽从旋转板的旋转中心径向向外指向，将树脂放置在工件附近的凹槽中， 并旋转旋转板以使树脂沿着凹槽的表面迁移并由此涂覆。

公开(公告)号：WO1993022726A1

公开(公告)日：1993-11-11

申请号：PCT/US1993004006

申请日：1993-04-28

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  WUNDERLICH, Russell, J. ,  TAYLOR, Mark ,  STANCIL, Charles, J. ,  HUNSAKER, Mikal, C. ,  BELMONT, Brian, V.

IPC: G06F12/06

CPC classification number: G06F12/0653 ,  G06F12/1433

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided. The RAM is only programmed once, with modifications to the RAM-provided write protect status and memory location values being made based on write protect and relocation status information contained in a separate register.

Abstract translation: 存储器映射和模块使能电路，用于允许为连接到存储器系统的任何模块中的任何位置定义逻辑128K字节的存储器块。 RAM由定义128千字节块的系统地址线寻址，输出数据为特定存储器模块提供行地址选通使能信号，以及将128K字节块放置在模块内所需的地址值。 各种其他参数，如写保护状态和存储器位置也由RAM提供。 提供了用于编程和读取RAM的电路和技术。 RAM仅被编程一次，修改RAM提供的写保护状态和存储位置值是基于单独寄存器中包含的写保护和重定位状态信息进行的。

公开(公告)号：WO1993013478A1

公开(公告)日：1993-07-08

申请号：PCT/US1992010953

申请日：1992-12-18

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  NEUFELD, E., David

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F3/0601 ,  G06F2003/0692 ,  G06F2211/1033 ,  G11B20/1833

Abstract: A method and apparatus for improving disk performance during partial stripe write operations in a computer system having a disk array subsystem utilizing parity fault tolerance technique. When a partial stripe write generation is begun, the method determines if the area or stripe where the write is to occur is unused space in the file system. If not, the partial stripe write operation is performed using a preceding read operation to read the current data and parity information from the disk as would normally be done. However, if the write area is unused space in the file system, then the contents of the data stripe do not need to be preserved. In this instance, the partial stripe write operation can be performed without any preceding read operations. By obviating the necessity of a preceding read operation, much of the performance penalty of doing a partial stripe write in the case where the rest of the data stripe does not need to be preserved is removed.

Abstract translation: 一种用于在具有使用奇偶校验容错技术的磁盘阵列子系统的计算机系统中的部分条带写入操作期间提高磁盘性能的方法和装置。 当开始部分条带写入生成时，该方法确定要发生写入的区域或条带是文件系统中的未使用空间。 如果不是，则使用前面的读取操作来执行部分条带写入操作，以如通常所做的那样从盘读取当前数据和奇偶校验信息。 但是，如果写入区域是文件系统中未使用的空间，则不需要保留数据条带的内容。 在这种情况下，可以在没有任何先前的读取操作的情况下执行部分条带写入操作。 通过消除前面的读取操作的必要性，消除了在不需要保留数据条带的其余部分的情况下进行部分条带写入的许多性能损失。

公开(公告)号：WO1993012480A1

公开(公告)日：1993-06-24

申请号：PCT/US1992010798

申请日：1992-12-14

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  ATKINSON, Lee, W.

IPC: G06F01/32

CPC classification number: G06F1/3215 ,  G06F1/3203 ,  G06F11/3409 ,  G06F11/3423 ,  G06F12/0802 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  Y02D10/126 ,  Y02D10/34

Abstract: A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.

Abstract translation: 电池供电的计算机系统通过监视与系统的操作相关联的各种事件来确定系统何时未使用。 该系统优选地监视高速缓存读取未命中和写入操作的数量，即，高速缓存命中率，并且当高速缓存命中率上升到高于某一水平时，降低系统时钟频率。 当高速缓存命中率高于一定水平时，可以假设处理器正在执行紧密循环，例如当处理器正在等待一个按键被按下时，可以在不影响系统性能的情况下降低频率。 或者，该装置监视存储器页面未命中，I / O写入周期或其他事件的发生，以确定计算机系统的活动级别。

公开(公告)号：WO1993010494A1

公开(公告)日：1993-05-27

申请号：PCT/US1992009875

申请日：1992-11-16

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  FAIRCHILD, Steven, E. ,  GEROCHE, Michael, R. ,  LUNDGREEN, Mark, T. ,  KLINGSPORN, Benny, J.

IPC: G06F11/26

CPC classification number: G06F11/2221 ,  G06F11/008 ,  G06F11/076 ,  G06F11/2205 ,  G06F11/3485 ,  G11B20/182

Abstract: A dynamic testing method for determining disk drive error rates based on the number of bytes which are read from a hard disk drive during test. The method identifies specific faulting disk sectors and disk error types and maintains a log of the errors. The method also accumulates the total number of bytes which have been read from the disk and determines whether the disk under test has exceeded acceptable error rates based on the number of bytes read during the test. This permits the method to identify a disk drive as having failed its test prior to completion of the full disk drive test cycle.

Abstract translation: 一种基于在测试期间从硬盘读取的字节数来确定磁盘驱动器错误率的动态测试方法。 该方法识别特定的故障磁盘扇区和磁盘错误类型，并维护错误日志。 该方法还会累积从磁盘读取的总字节数，并根据测试期间读取的字节数，确定被测磁盘是否超过可接受的错误率。 这样就可以在完成磁盘驱动器测试周期之前将该磁盘驱动器识别为未通过测试。